The PXIe-5840 has multiple clocks available on the device and inside the FPGA. The main device clock is the Sample Clock, which is used to clock the ADC, clock the DAC, and create the Data Clock for the related FPGA logic.

Sample Clock

The Sample Clock runs at 1.25 GHz and is exported by the phase-locked loop (PLL).

You can select one of the following resources as the reference signal for the PLL:

  • The internal temperature compensated crystal oscillator (TCXO)
  • The REF IN front panel connector
  • PXI_CLOCK

While the Sample Clock frequency is fixed at 1.25 GHz, you can achieve high-resolution I/Q data rates using the Fractional Interpolator and Fractional Decimator DSP FPGA VIs.

Data Clock

The Sample Clock is divided by eight to create the Data Clock, which is sent to the FPGA.

The Data Clock runs at 156.25 MHz, and it is the main clock used for the acquisition and generation data paths inside the FPGA. Because the Data Clock is one-eighth the rate of the Sample Clock, eight samples are processed on each cycle of the Data Clock.



FPGA Clocks

The following table lists the clocks available in the FPGA. In addition to these clocks, LabVIEW FPGA allows for derived clocks at user-defined frequencies.

Name Frequency (MHz) Description
Data Clock 156.25 Main clock used for the acquisition and generation data paths in the FPGA.
Data Clock x2 312.5 In-phase with the Data Clock and used for DSP VIs.
Data Clock x4 625 In-phase with the Data Clock.
40 MHz Onboard Clock 40 Free-running 40 MHz oscillator.
200 MHz Onboard Clock 200 Free-running 200 MHz oscillator.
PXIe_CLK100 100 100 MHz clock from the backplane.

Front Panel Clocking Connectors

You can use the PXIe-5840 REF IN front panel connector to apply an external 10 MHz reference to the device.