Interconnecting the Modules

Note This module configuration frequency-locks to the PXIe-5653100 MHz onboard Reference Clock by daisy chaining the 100 MHz Reference Clock to slave digitizer modules. To frequency-lock to the PXI backplane, the PXIe-5653 requires an OCXO-quality timebase source present on the PXI backplane.

For the best long-term phase stability over temperature, use the PXI backplane as the Reference Clock source, but override the native PXI chassis backplane clock with an OCXO-quality timebase that meets the requirements listed in the PXIe-5665 Specifications. The PXIe-5665 cannot lock to the native PXI chassis backplane clock, and attempting to do so without overriding it with an OCXO timebase results in phase-locked loop (PLL) lock errors. The PXIe-6674T Timing and Multichassis Synchronization module is an option for synchronizing multiple digitizer clocks. The PXIe-6674T10 MHz clock can be driven onto the PXI backplane when placed in the chassis System Timing Slot, also known as the Star Trigger Controller Slot. You can also connect the output of the PXIe-6674T10 MHz clock to the 10 MHzBNC IN terminal on the back of the PXI chassis from any PXI chassis slot using an SMA-to-BNC cable.