FPGA Clocks

The following table lists the clocks available in the FPGA. In addition to these clocks, LabVIEW FPGA allows for derived clocks at user-defined frequencies.

Name Frequency (MHz) Description
Sample Clock 120 Main clock used for the ADC, DAC, and I/Q data paths in the FPGA. Also the reference signal for the RF IN and RF OUT LO circuits.
Sample Clock x2 240 In-phase with the Sample Clock.
Sample Clock x3 360 In-phase with the Sample Clock and used for some DSP VIs.
40 MHz Onboard Clock 40 Free-running 40 MHz oscillator.
125 MHz Onboard Clock 125 Free-running 125 MHz oscillator.
133 MHz Onboard Clock 133 Derived from the 40 MHz oscillator.
200 MHz Onboard Clock 200
PXIe_CLK100 100 100 MHz clock from the backplane.
DIO Clk In User-defined, ≤125 MHz Can be externally supplied on the DIGITAL I/O front panel connector.