ADCs and DACs

The ADCs and DACs are clocked at 120 MS/s to provide 80 MHz of complex bandwidth, and high-resolution I/Q data rates are achieved by using the Fractional Interpolator and Fractional Decimator DSP FPGA VIs. The ADCs and DACs are automatically synchronized to the Sample Clock domain inside the FPGA, which allows for interfacing to both the ADCs and DACs in the same clock domain with full synchronization.