PXI Triggers

You can use the FPGA I/O Node to access the eight PXI trigger lines, eight PFI lines, and two DSTAR differential trigger lines on the PXIe-5170/5171. The Data Trigger instrument design library contains IP that can operate on signals received on any of these trigger resources.

PXI Trigger lines are bussed across the backplane to all peripheral devices, so they must be reserved by the application to prevent double-driving the lines and potentially damaging third-party PXI Express devices.

Since the eight PXI trigger lines are bidirectional signals, their configuration must include a direction control, which is accessed through an I/O Method. Alternately, PXIe_DStar_B is a dedicated point-to-point signal driven from the System Timing Module slot while PXIe_DStar_C is a dedicated point-to-point signal driven to the System Timing Module slot.

When developing an FPGA VI that uses these trigger resources, reserve the trigger lines you are using to ensure compatibility with other NI devices. Refer to the PXI Specifications Tutorial for more information about trigger bus requirements.