Clocks

Note   This functionality is only available when using instrument design libraries.

The following table lists the clocks available in the FPGA. In addition to these clocks, LabVIEW FPGA allows for derived clocks at user-defined frequencies, using these clocks as references. Not all clock sources may be used to derive clocks. For more information on how to create a derived clock, refer to the Creating FPGA-Derived Clocks topic in the LabVIEW FPGA Module Help.

Note   The clocks in this table are available only when programming the FPGA target using LabVIEW FPGA and the instrument design libraries.
Name Frequency (MHz) Supports Derived Clocks? Description
40 MHz Onboard Clock 40 Yes Free-running 40 MHz oscillator.
PXIe_Clk100 100 Yes 100 MHz clock from the backplane.
Data Clock 125 No ADC Clock (Sample Clock) divided in hardware by 2, provided to the ADC interface and LabVIEW FPGA, and used by the instrument design libraries. For more information on Sample Clock sources, refer to the Clocking section.
Data Clock x2 250 No Data clock multiplied by two. This clock is useful for running overclocked DSP. For more information on Sample Clock sources, refer to the Clocking section.
Data Clock x3 375 No Data clock multiplied by three. This clock is useful for running overclocked DSP. For more information on Sample Clock sources, refer to the Clocking section.
PXIe_DStarA 120 to 250 Yes External backplane clock driven by the System Timing Module.