Each channel requires a Force and Sense connection. Channel connection pairs are indicated on the PXIe-4133 front panel.

The following figure illustrates channel connections to a diode test fixture. Note that, on the test fixture, the Force and Sense connections should be made as close to the diode as possible.

Figure 1. Wiring the PXIe-4133 to a Diode Test Fixture


Voltage Limits Related to Force LO

There are specific voltage limits for the Sense HI and Sense LO inputs concerning the Force LO terminal:

  • Sense LO to Force LO—0 V to +2 V maximum. The cable resistance from Force LO to the VCSEL must cause a voltage drop of less than 2 V during maximum current pulses.
  • Sense HI to Force LO—0 V to +15.6 V maximum. The combined voltage drop across the Force LO cable and the forward voltage of the VCSEL must not exceed 15.6 V.

    • Cabling Considerations

    For best performance, take voltage measurements as close as possible to the DUT.

    Cable inductance can cause large measurement or pulse output errors when generating narrow current pulses with fast slew rate. Parasitic capacitance between HI and LO connections may slow voltage breakdown measurements​. Use the recommended triaxial cables to mitigate these considerations.

    Sense connections may not require these recommended cables. However, parasitic capacitance between sense HI and sense LO connections can slow voltage breakdown measurements. Use the recommended triaxial cables to mitigate this consideration.