Hardware State Diagram

The following figure shows the acquisition engine state diagram for the IF digitizer in your vector signal analyzer. This state diagram models the PXI-5661 when it acquires data in the I/Q mode.


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Arrow Color Indication
Blue State transitions always caused by software
Black State transitions caused by the internal state machine of the device
Red Output signals
Orange User-configurable state transitions caused by software or hardware

Basic Hardware States

Many digitizers share a common digital architecture called Synchronization and Memory Core (SMC). SMC-based digitizers can be in any of the following basic states during the course of operation.

  • Idle—The module is not sampling a waveform. All the session attributes are programmable in this state. In this state, the attributes have not necessarily been applied to hardware yet, so the hardware configuration of the module may not match the session attribute values. Also, the module remains configured as it was the last time a session was committed. When you call Initiate, all the attributes are programmed to the hardware. If you recently reset the computer, the module is in the Idle state.
  • Wait for Start Trigger—The module transitions to this state when you initiate an acquisition. If the Start Trigger source is configured as None, the module immediately transitions from this state and generates a Start Trigger. If you configure the Start Trigger source as a software or hardware trigger from one of the available sources, the module remains in this state until the configured trigger occurs. When the module recognizes a trigger condition, it transitions from this state on the next clock cycle and generates a Start Trigger. The default Start Trigger source is None.
  • Minimum Pre-Reference Trigger Sampling—The module can transition into this state two ways: receiving the Start Trigger from the Start Trigger source or receiving the Advance trigger from the Advance trigger source. The transition into this state depends on the previous state of the module. While in this state, the module samples according to the session attributes configured. The module remains in this state until three conditions are satisfied: the minimum Pre-Reference trigger sampling completes, the time-to-digital converter (TDC) is ready, and the trigger-to-trigger delay has expired. The first time through this state, the trigger-to-trigger delay does not have an effect. When the three conditions are satisfied, the module transitions from this state on the next clock cycle. Use the Pretrigger Samples property or NIRFSA_ATTR_REF_TRIGGER_PRETRIGGER_SAMPLES attribute to specify the number of samples to be acquired before the Reference Trigger is received.
  • Wait for Arm Reference Trigger while Sampling —After the module finishes the Minimum Pre-Reference Trigger Sampling state, the module transitions into this state. While in this state, the module continues to acquire Pre-Reference trigger samples according to the session attributes configured. If you configure the Arm Reference trigger source as None, the module transitions from this state on the next clock edge. If you configure the Arm Reference trigger source as a software trigger or a hardware trigger from one of the available sources, the module remains in this state until the configured trigger occurs. When the module recognizes a trigger condition, the module transitions from this state. The default Arm Reference trigger source is None.
  • Wait for Reference Trigger while Sampling—After the module receives Arm Reference trigger from the Arm Reference trigger source, the module transitions into this state. If you configure the Reference trigger Source as a software or hardware trigger from one of the available sources, the module remains in this state until the configured trigger occurs. When the module recognizes a trigger condition, the module transitions from this state. The default Reference trigger source is None.
  • Post-Reference Trigger Sampling—After the module receives the Reference trigger, the module transitions into this state. At the beginning of this state, the module starts a trigger-to-trigger delay counter. You can configure this delay counter using Reference Trigger Delay property and the NIRFSA_ATTR_REF_TRIGGER_DELAY attribute to delay the module from looking for a Reference trigger between records. At the same time, the trigger-to-trigger delay counter is started, the module begins sampling Post-Reference trigger samples according to the session attributes configured. When the Post-Reference trigger sampling is completed, the module transitions from this state.
  • Record Complete—After the module completes Post-Reference trigger sampling state, the module transitions into this state. The module leaves this state after the current record has been stored in the onboard memory. Upon leaving this state, the module generates an End of Record Event.
  • Wait for Advance Trigger—After the module has completed a record and determines that there are still more records to complete, the module transitions into this state. If you configure the Advance Trigger source as None, the module transitions from this state on the next clock edge. If you configure the Advance Trigger source as a software or hardware trigger from one of the available sources, the module remains in this state until the configured trigger occurs. Upon the module recognizing a trigger condition, the module transitions from this state. The default Advance Trigger source is None.
  • Done—After the module completes a record and determines that all the records are done, it transitions into this temporary state. Upon entering this state, the module generates the End of Acquisition Event. The software transitions the module from this state and back to the Idle state when you call either a Fetch or Check Status VI or function.