Timing and Synchronization

Timing Signals

DSA devices feature the following timing signals.

Frequency Timebase

DSA devices have high-accuracy oscillators on board. The oscillator feeds a direct digital synthesis (DDS) chip, which is used to generate the other on-board timing signals.

Reference Clock

PXI/PXIe chassis backplanes provide a common, 10 MHz reference clock to each peripheral slot. An independent buffer drives the clock signal to each device in the chassis.

DSA devices that support reference clock synchronization are able to lock their frequency timebases to this shared reference.

You can drive PXI_CLK10 from an external source through the PXI_CLK_IN pin on the P2 connector of the star trigger slot on the chassis. Driving an external clock source on this pin automatically disables the 10 MHz source generated on the PXI/PXIe backplane.

Oversample Clock

The delta-sigma converters used on DSA devices acquire 1-bit samples at a rate that is much faster than the requested sample rate. The resulting 1-bit data stream is converted to a 24-bit data stream at the requested sample rate. The oversample clock drives the acquisition of 1-bit samples from the delta-sigma converter. The frequency of the oversample clock is a multiple of the requested sample rate.

Sample Clock Timebase

The sample clock timebase is the timing signal that is used to produce the oversample clock on DSA devices. All of the converters on a single DSA device share a common sample clock timebase.

When a DSA device is operating stand-alone (without synchronizing to other devices), a DDS chip produces the sample clock timebase. DDS is a method of generating a programmable clock with excellent frequency resolution. The DDS chips are capable of between 28- and 32-bits of resolution, and can produce between 228 and 232 frequency steps to create the sample clock timebase.

When synchronizing multiple DSA devices, each device must share a common sample clock timebase. When multiple devices share a common sample clock timebase, each is able to generate a phase-aligned version of the ADC and DAC oversample clocks. This allows for tight synchronization between multiple devices. There are two methods available to share a common sample clock timebase:

  • Generate the sample clock timebase on a master device. Route the generated timebase to all slave devices. Refer to Master Sample Clock Timebase Synchronization for more information.
  • Configure each DSA device to generate its own sample clock timebase. Lock the frequency timebase on each device to the reference clock provided by the backplane. At this point, a sync pulse can be distributed to each device. This will automatically phase-align the generated sample clock timebase on each device. Refer to PXI/PXIe Reference Clock Synchronization for more information.

The ratio between the sample rate (fs) and sample clock timebase rate (ftb) can have one of several values. Refer to the specifications for your product for more information.

The sample clock timebase has stringent requirements for frequency and stability. DSA devices do not accept arbitrary clock signals from external sources such as encoders or tachometers. However, signal processing features in the Sound and Vibration Measurement Suite often provide an excellent alternative to external clocking in encoder and tachometer applications. Visit ni.com/soundandvibration for more information about the Sound and Vibration Measurement Suite.

Note (USB-4431 and PCI/PXI-4461) You can run input and output operations simultaneously at different rates on these devices and modules. However, because the timing information for all operations is derived from a common sample clock timebase, the ratio between every input and output rate must be a power of 2. For example, assume that the input sample rate is 8 kS/s. Valid output update rates include, but are not limited to, 2 kS/s, 8 kS/s, 16 kS/s, and 64 kS/s. In this case, 20 kS/s is not a valid output update rate, because the ratio between 8 kS/s and 20 kS/s is not a power of 2.

Sync Pulse

The sync pulse is used with DSA synchronization. It has two purposes:

  • It resets the DDS chips and clock dividers on each DSA device at the same instant. This aligns the sample clock timebase signals (when using reference clock synchronization) and the oversample clocks on each device.
  • It resets the ADCs and DACs on each DSA device at the same instant. This aligns the ADCs and DACs.

When synchronizing multiple DSA devices, one device must export a sync pulse, and all other devices must import it. This allows each device in the system to be reset simultaneously.

Start Trigger

When synchronizing multiple DSA devices, each device must start acquiring (and generating) data simultaneously. To align the acquisition and generation events, one device must export a start trigger, and all other devices must import it.

Sample Rate and Update Rate, Accuracy and Coercion

On DSA devices, a DDS chip produces the sample clock timebase. DDS is a method of generating a programmable clock with excellent frequency resolution. The DDS chip takes as an input another higher frequency clock called the frequency timebase. All of the timing signals on a device are derived from the sample clock timebase.

When using a DSA device, you specify the sample and update rates that the device will use when acquiring and generating samples. However, the device will never run at exactly the rate you request. The difference between the requested rate and the actual rate depends on two factors:

  • The accuracy of the frequency timebase (the input to the DDS chip)
  • The frequency resolution of the DDS chip

The accuracy of the frequency timebase usually dominates the frequency resolution of the DDS chip, especially if the internal frequency timebase is used. However, in some applications, it is useful to understand the effect of the frequency resolution of the DDS chip.

Suppose that the frequency timebase on a DSA device has no error. There will still be a small error between the actual and requested rates, because DDS chips do not have unlimited frequency resolution. For example, if you request that a PXI-4461 acquire data at 200 kS/s, NI-DAQmx automatically coerces the sample rate to a slightly higher value of 200.0000000407 kS/s. This process is transparent, although NI-DAQmx allows you to query the coerced sample or update rate by reading the SampClk.Rate NI-DAQmx Timing property. The returned value does not take into account errors in the frequency timebase.

Calculating the Coerced Rate

To calculate the coerced rate, use the following steps:

  1. Calculate the frequency of the sample clock timebase (the DDS chip output) needed to run at the requested rate.
  2. Calculate the value of the tuning word needed to run at the requested rate. The tuning word is a 28- or 32-bit integer that is programmed into the DDS chip in order to set the desired sample clock timebase frequency. In almost all cases, the calculated tuning word is not an integer. This signifies that the DDS chip cannot generate the exact sample clock timebase frequency that is needed to run at the requested rate. In this case, NI-DAQmx rounds the calculated tuning word to the next highest integer. Therefore, the coerced rate is slightly higher than the requested rate.
  3. Using the rounded tuning word, calculate the actual frequency of the sample clock timebase.
  4. Using the actual frequency of the sample clock timebase, calculate the actual rate that the DSA device will use when acquiring or generating samples.

Calculate the Frequency of the Sample Clock Timebase

Use the following tables to determine the rate multiplier. The rate multiplier depends on the desired rate, the device being used, and, if using an NI 447x, whether enhanced low-frequency alias rejection is enabled. The rate multiplier is also used to calculate the actual sample or update rate. Refer to Calculate the Actual Sample or Update Rate.

Table 10. USB-443x Rate Multipliers
Rate (kS/s) Rate Multiplier
0.8 ≤ fs < 1.6 215
1.6 ≤ fs < 3.2 214
3.2 ≤ fs < 6.4 213
6.4 ≤ fs < 12.8 212
12.8 ≤ fs < 25.6 211
25.6 ≤ fs < 51.2 210
51.2 ≤ fs ≤ 102.4 29
Table 11. PCI/PXI-446x Rate Multipliers
Rate (kS/s) Rate Multiplier
1.0 ≤ fs ≤ 1.6 214
1.6 < fs ≤ 3.2 213
3.2 < fs ≤ 6.4 212
6.4 < fs ≤ 12.8 211
12.8 < fs ≤ 25.6 210
25.6 < fs ≤ 51.2 29
51.2 < fs ≤ 102.4 28
102.4 < fs ≤ 204.8 27
Table 12. PXI/PXIe-449x Rate Multipliers
Rate (kS/s) Rate Multiplier
0.1 ≤ fs ≤ 0.2 217
0.2 < fs ≤ 0.4 216
0.4 < fs ≤ 0.8 215
0.8 < fs ≤ 1.6 214
1.6 < fs ≤ 3.2 213
3.2 < fs ≤ 6.4 212
6.4 < fs ≤ 12.8 211
12.8 < fs ≤ 25.6 210
25.6 < fs ≤ 51.2 29
51.2 < fs ≤ 102.4 28
102.4 < fs ≤ 204.8 27

Use the following equation to determine the frequency of the sample clock timebase.

SampTimebaseRate = Rate × RateMultiplier

where

Rate is the desired sample or update rate.

RateMultiplier is the rate multiplier value from the preceding Rate Multipliers tables.

Calculate the DDS Tuning Word

Determine the frequency of the frequency timebase (the input clock to the DDS), the number of bits in the DDS, and the size of the external clock multiplier on the device being used by using the following table. These values are also used in Calculate the Actual Frequency of the Sample Clock Timebase.

Table 13. Clock Properties On DSA Devices
Model Nominal Frequency of Frequency Timebase (MHz) Number of DDS Bits External Clock Multiplier
USB-443x 48.0 28 6
PCI/PXI-446x 100.0 32 1
PXI/PXIe-449x

Use the following equation to determine the DDS tuning word.

TuningWord = ceiling ( S a m p T i m e b a s e R a t e E x t e r n a l M u l t × 2 D d s B i t s F r e q T i m e b a s e R a t e ) TuningWord = ceiling ( S a m p T i m e b a s e R a t e E x t e r n a l M u l t × 2 D d s B i t s F r e q T i m e b a s e R a t e )

where

SampTimebaseRate is the frequency of the sample clock timebase (calculated in Calculate the Frequency of the Sample Clock Timebase).

ExternalMult, DdsBits, and FreqTimebaseRate are the values from the preceding Clock Properties on DSA Devices table.

The ceiling function rounds a number to the next highest integer. For example, ceiling(1.1) = 2, and ceiling(2.0) = 2.

Calculate the Actual Sample or Update Rate

Use the following equation to determine the actual frequency of the sample clock timebase.

A c t S a m p T i m e b a s e R a t e = T u n i n g W o r d 2 D d s B i t s × FreqTimebaseRate × ExternalMult A c t S a m p T i m e b a s e R a t e = T u n i n g W o r d 2 D d s B i t s × FreqTimebaseRate × ExternalMult

where

TuningWord is the DDS tuning word that was calculated in Calculate the DDS Tuning Word.

ExternalMult, DdsBits, and FreqTimebaseRate are the values from the Clock Properties on DSA Devices table.

Calculate the Actual Frequency of the Sample Clock Timebase

Use the following equation to determine the actual sample or update rate.

A c t R a t e = A c t S a m p T i m e b a s e R a t e R a t e M u l t i p l i e r A c t R a t e = A c t S a m p T i m e b a s e R a t e R a t e M u l t i p l i e r

where

ActSampTimebaseRate is the actual sample clock timebase rate calculated in Calculate the Actual Frequency of the Sample Clock Timebase.

RateMultiplier is the rate multiplier value from the Rate Multipliers tables.

Example of Calculating the Coerced Rate

The following table lists the rates that different DSA devices and modules will actually sample at if configured to run at one of several different rates. This assumes that the frequency timebase is running at exactly the nominal rate.

Table 14. Coerced Sample and Update Rates on DSA Devices (kS/s)
Desired Rate (kS/s) DSA Device/Module
USB-443x PCI/PXI-446x PXI/PXIe-449x
1.0 1.0000000111 1.000000000317
20.0 20.000000484 20.0000000177
80.0 80.00000194 80.0000000709
100.0 100.000000326 100.0000000204

The following equations show how a 1 kS/s sample rate on an PXI-4461 is coerced to a slightly higher value.

Calculate the Frequency of the Sample Clock Timebase

From the PCI/PXI-446x Rate Multipliers table, the rate multiplier at the 1 kS/s sample rate is 214. Therefore, the frequency of the sample clock timebase is:

SampTimebaseRate = Rate × RateMultiplier

16.348 MHz = 1 kS/s × 214

Calculate the DDS Tuning Word

From the Clock Properties on DSA Devices table, the frequency of the frequency timebase on the PXI-4461 is 100.0 MHz, the DDS has 32 bits, and the external clock multiplier is 1. The sample clock timebase frequency calculated in the previous equation is 16.384 MHz when sampling at 1 kS/s. Therefore, the tuning word is:

TuningWord = ceiling ( S a m p T i m e b a s e R a t e E x t e r n a l M u l t × 2 D d s B i t s F r e q T i m e b a s e R a t e ) TuningWord = ceiling ( S a m p T i m e b a s e R a t e E x t e r n a l M u l t × 2 D d s B i t s F r e q T i m e b a s e R a t e )
703 , 687 , 442 = ceiling ( 16.384 ⁢ M H z 1 × 2 32 100.0 ⁢ M H z ) 703 , 687 , 442 = ceiling ( 16.384 ⁢ M H z 1 × 2 32 100.0 ⁢ M H z )

Calculate the Actual Frequency of the Sample Clock Timebase

The frequency of the frequency timebase on the PXI-4461 is 100.0 MHz, the DDS has 32 bits, and the external clock multiplier is 1. The tuning word calculated in the previous equation is 703,687,442 when sampling at 1 kS/s. Therefore, the actual frequency of the sample clock timebase is:

A c t S a m p T i m e b a s e R a t e = T u n i n g W o r d 2 D d s B i t s × FreqTimebaseRate × ExternalMult A c t S a m p T i m e b a s e R a t e = T u n i n g W o r d 2 D d s B i t s × FreqTimebaseRate × ExternalMult
16.38400000520 ⁢ M H z = 703 , 687 , 442 2 32 × 100.0 ⁢   M H z × 1 16.38400000520 ⁢ M H z = 703 , 687 , 442 2 32 × 100.0 ⁢   M H z × 1

Calculate the Actual Sample or Update Rate

The rate multiplier on the PXI-4461 at the 1 kS/s sample rate is 214. From the previous equation, the actual frequency of the sample clock timebase is 16.38400000520 MHz. Therefore, the actual sample rate is:

A c t R a t e = A c t S a m p T i m e b a s e R a t e R a t e M u l t i p l i e r A c t R a t e = A c t S a m p T i m e b a s e R a t e R a t e M u l t i p l i e r
1.000000000317 ⁢ k S / s = 16.38400000520 ⁢ M H z 2 14 1.000000000317 ⁢ k S / s = 16.38400000520 ⁢ M H z 2 14

Synchronization

(PCI/PXI-446x and PXI/PXIe-449x) NI-DAQmx can automatically synchronize multiple DSA devices to run at the same rate as each other. Just add channels from multiple devices to the same NI-DAQmx task, and NI-DAQmx will automatically control clock sharing and sync pulse routing.

The following methods show how you can add channels from multiple devices to the same NI-DAQmx task.

  • When using the DAQ Assistant, you can select more than one physical channel at a time, or you can click the Add Channels button to add additional channels.
  • When creating a task programmatically, you can specify a physical channel string containing channels from multiple devices, such as PXI1Slot2/ai0:7,PXI1Slot3/ai0:7.
  • You can also call the NI-DAQmx Create Channel VI multiple times on the same task, specifying different channels for each call. This allows you to use multiple measurement types, such as acceleration, sound, pressure, and voltage in the same task.

    Some applications require tight synchronization between input and output operations on multiple devices. Synchronization is important to minimize skew between channels or to eliminate clock drift between devices in long-duration operations. You can synchronize the analog input and output operations on two or more DSA devices to extend the channel count of DSA measurements. The following table lists possible DSA device synchronization configurations to help you decide the method of synchronization to use.

Note (USB-443x) USB-443x devices do not support synchronization.
Table 15. Supported DSA Module Synchronization Configuration
Configuration Reference Clock Synchronization (PXI/PXIe Only) Master Sample Clock Timebase Synchronization*,†
PXI/PXIe-449x and PXI/PXIe-449x Supported —
PCI/PXI-446x and PCI/PXI-446x Supported Supported
PXI/PXIe-449x and PCI/PXI-446x Supported —
PXI/PXIe-449x and PXIe-4330/4331‡ Supported —

* PXI DSA modules with an eHM (PXI hybrid compatible) backplane connector do not support master sample clock timebase synchronization.

† When using master sample clock timebase synchronization in a PXIe chassis, all DSA modules must be slaves. A timing module capable of driving the PXI Star and trigger lines must be the master.

‡ NI-DAQmx 9.1 and later support synchronizing PXIe-4330/4331 bridge modules with PXIe-449x modules using reference clock synchronization. The PXIe-4330/4331 module must be the master.

Refer to Developing Your Dynamic Signal Acquisition Application for more information about developing synchronization applications with DSA devices.

Reference Clock Synchronization (PXI/PXIe Only)

With reference clock synchronization, master and slave devices lock their frequency timebases (the inputs of their DDS chips) to the PXI_CLK10 signal (the 10 MHz clock supplied by the PXI/PXIe backplane). This is accomplished by using phase-locked loop (PLL) circuitry. After the inputs of the DDS chips on each device are phase-aligned, a sync pulse is sent, which aligns the sample clock timebase on each device (the output of each DDS chip), the oversample clocks, and the ADCs and DACs. Finally, a shared start trigger is sent, which starts the acquisition and generation events on each device at the same instant.

When using this method of synchronization, master and slave devices can be placed in any slot in the PXI/PXIe chassis. You can synchronize all devices in the chassis.

After you install the DSA devices in the chassis, complete these steps to synchronize the hardware:

  1. Specify PXI_CLK10 as the reference clock source for all devices to force the DSA devices to lock to the reference clock on the PXI/PXIe chassis.
  2. Choose an arbitrary master device to issue a sync pulse on one of the PXI/PXIe Trigger lines. The sync pulse aligns all the clocks in the system to within nanoseconds and also resets the ADCs and DACs.
  3. Read the SyncPulse.SyncTime NI-DAQmx Timing property on all of the devices that are importing the sync pulse. Calculate the maximum value, and write it to the SyncPulse.MinDelayToStart NI-DAQmx Timing property on the device that is exporting the sync pulse.
  4. Configure one of the DSA devices in the system to export its start trigger on one of the PXI/PXIe trigger lines.

    If possible, configure the device that is exporting the sync pulse to also export the start trigger. However, if the application demands it, separate devices can export the sync pulse and start trigger. In this case, the configuration information for all the devices that are importing the sync pulse must be manually committed prior to starting any of the devices. To manually commit a task, use the NI-DAQmx Control Task VI with a value of commit wired to the action control.

  5. Start all of the devices that are importing the start trigger by using the NI-DAQmx Start Task VI. Finally, start the device that is exporting the start trigger. This will cause all devices in the system to start acquiring and generating data simultaneously.

Consider the following caveats to using reference clock synchronization:

  • Not all DSA devices support low-frequency alias rejection. When you synchronize multiple DSA devices, you must verify that all the devices share the same low-frequency alias rejection setting. You can enable low-frequency alias rejection if all of the DSA devices in the system support it. Disable low-frequency alias rejection on all devices when at least one DSA device does not support it.
  • Inherent delays exist between different families of DSA devices. You might need to compensate for filter delay in the waveforms when you synchronize between device families.
  • At very low sample rates, you might notice that it takes several seconds for an acquisition to begin. This is because during the sync pulse, the ADCs get reset and require many sample clock cycles before they are operational. The reset process takes longer when slower sample clocks are used. To improve the time it takes an acquisition to begin, select a higher sample rate or enable low-frequency alias rejection on all devices, if possible. This causes the ADCs to run at a higher sample rate, while the onboard firmware decimates the data back to your low sample rate.
  • For configurations that specify multiple sample rates between different devices, all rates must be related by a power of two. For example, if one device has a sample rate of 100 kS/s, the other devices can run at 50 kS/s, 25 kS/s, or 200 kS/s but not at 40 kS/s. The slowest running device in the system must export the start trigger. Because the delta sigmas run at different rates, you have different filter delays among all devices running at different rates.

Master Sample Clock Timebase Synchronization

With master sample clock timebase synchronization, one master device exports its master sample clock timebase signal to all the other devices in the system. Next, a sync pulse is sent, which phase-aligns all the oversample clocks on all the devices, as well as the ADCs and DACs. Finally, a shared start trigger is sent, which starts the acquisition and generation events on each device at the same instant.

For a PXI/PXIe system, the master device must reside in the master timebase slot of the chassis, because the master timebase slot has specific point-to-point routing, called PXI Star, to the other peripheral slots on which it exports the clock. For a PXIe chassis, all DSA devices must be slaves. A timing module capable of driving the PXI Star and trigger lines must be the master. A PXI system cannot synchronize devices with master sample clock timebase synchronization beyond slot 14. PXIe systems can synchronize all peripheral slots to the master sample clock timebase. For PCI devices, the clock is physically exported through a RTSI cable that you must attach to the back of all the synchronized devices in the system.

After you install the DSA devices, complete the following steps to synchronize the hardware.

  1. Program the master device to export its sample clock timebase to all the slave devices. This shared clock guarantees that all ADC and DAC clocks share the same oversample clock. The signal is routed on PXI Star for PXI/PXIe systems and any of the RTSI lines for PCI systems. The default RTSI line is 8.
  2. Program the master device to route a sync pulse to all the slave devices. For PXI/PXIe systems, you can use any of the PXI/PXIe trigger lines to route a sync pulse to all slave devices. For PCI devices, the default RTSI line is 9, but you can program another RTSI line. The sync pulse aligns all the clocks in the system to within nanoseconds and also resets the ADCs and DACs.
  3. Read the SyncPulse.SyncTime NI-DAQmx Timing property on all of the devices that are importing the sync pulse. Calculate the maximum value, and write it to the SyncPulse.MinDelayToStart property on the device that is exporting the sync pulse.
  4. Configure one of the DSA devices in the system to export its start trigger on one of the PXI/PXIe trigger lines for a PXI/PXIe system, or one of the RTSI lines 0 to 6 for a PCI system.

    If possible, configure the device that is exporting the sync pulse to also export the start trigger. However, if the application demands it, separate devices can export the sync pulse and start trigger. In this case, the configuration information for all the devices that are importing the sync pulse must be manually committed prior to starting any of the devices. To manually commit a task, use the NI-DAQmx Control Task VI with a value of commit wired to the action control.

  5. Start all of the devices that are importing a start trigger by using the NI-DAQmx Start Task VI. Finally, start the device that is exporting the start trigger. This will cause all devices in the system to start acquiring and generating data simultaneously.

Consider the following caveats to using master sample clock timebase synchronization:

  • Not all DSA devices support low-frequency alias rejection. When you synchronize multiple DSA devices, you must verify that all the devices share the same low-frequency alias rejection setting. You can enable low-frequency alias rejection if all of the DSA devices in the system support it. Disable low-frequency alias rejection on all devices when at least one DSA device does not support it.
  • Inherent delays exist between different families of DSA devices. You might need to compensate for filter delay in the waveforms when you synchronize between device families.
  • At very low sample rates, you might notice that it takes several seconds for an acquisition to begin. This is because during the sync pulse, the ADCs get reset and require many sample clock cycles before they are operational. The reset process takes longer when slower sample clocks are used. To improve the time it takes an acquisition to begin, select a higher sample rate or enable low-frequency alias rejection on all devices, if possible. This causes the ADCs to run at a higher sample rate, while the onboard firmware decimates the data back to your low sample rate.
  • For configurations that specify multiple sample rates between different devices, the rates on all devices must be related by a power of two. Moreover, the slave devices must not run faster than the master device. For example, if the master device has a sample rate of 100 kS/s, the slave devices can run at 50 kS/s or 25 kS/s, but not at 40 kS/s or 200 kS/s. The slowest running device in the system must export the start trigger. Because the delta-sigmas run at different rates, you have different filter delays among all devices running at different rates.