PCI/PCIe/PXI/PXIe/USB-6251 Specifications

PCI/PCIe/PXI/PXIe/USB-6251 Specifications

These specifications apply to the PCI/PCIe/PXI/PXIe/USB-6251.

All specifications are subject to change without notice.

The following specifications are typical at 25 °C, unless otherwise noted.

Notice The protection provided by the PCI/PCIe/PXI/PXIe/USB-6251 can be impaired if it is used in a manner not described in this document.

Revision History

Version Date changed Description
375213E-01 October 2025 Updated I/O connector specifications.
375213D-01 June 2025 Added pinout diagrams.
375213C-01 October 2015 Updated environmental and legal information.
375213B-01 September 2015 Updated formatting.
375213A-01 February 2015 Initial release (PCI/PCIe/PXI/PXIe/USB-6251 only).
371291H-01 Original specifications document: NI 625x Specifications. Original specifications document: NI 625x Specifications.

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Device Pinouts

Figure 1. NI PCI/PCIe/PXI/PXIe-6251 Pinout


Figure 2. NI USB-6251 Screw Terminal Pinout


Figure 3. NI USB-6251 BNC Front Panel and Pinout


Figure 4. NI USB-6251 Mass Termination Pinout


Analog Input

Table 2. Analog Input
Number of channels 8 differential or 16 single ended
ADC resolution 16 bits
DNL No missing codes guaranteed
INL Refer to AI Absolute Accuracy
Timing resolution 50 ns
Timing accuracy 50 ppm of sample rate
Input coupling DC
Input range ±0.1 V, ±0.2 V, ±0.5 V, ±1 V, ±2 V, ±5 V, ±10 V
Maximum working voltage for analog inputs (signal + common mode) ±11 V of AI GND
CMRR (DC to 60 Hz) 100 dB
Input bias current ±100 pA
Small signal bandwidth (-3 dB) 1.7 MHz
Input FIFO size 4,095 samples
Scan list memory 4,095 entries
Table 3. AI Sample Rate
Single channel maximum 1.25 MS/s
Multichannel maximum (aggregate) 1.00 MS/s
Minimum No minimum
Table 4. AI Input Impedance
Device on, AI+ to AI GND >10 GΩ in parallel with 100 pF
Device on, AI- to AI GND >10 GΩ in parallel with 100 pF
Device off, AI+ to AI GND 820 Ω
Device off, AI- to AI GND 820 Ω
Table 5. AI Crosstalk (at 100 kHz)
Adjacent channels -75 dB
Non-adjacent channels -95 dB
Table 6. AI Data Transfers
PCI/PCI Express/PXI/PXI Express DMA (scatter-gather), interrupts, programmed I/O
USB USB Signal Stream, programmed I/O
Table 7. AI Overvoltage Protection for All Analog Input and Sense Channels
Device on ±25 V for up to four AI pins
Device off ±15 V for up to four AI pins
Table 8. AI Input Current During Overvoltage Condition
Input current during overvoltage condition ±20 mA maximum/AI pin

Settling Time for Multichannel Measurements

Table 9. Settling Time for Multichannel Measurements
Range ±60 ppm of Step (±4 LSB for Full-Scale Step) ±15 ppm of Step (±1 LSB for Full-Scale Step)
±1 V, ±2 V, ±5 V, ±10 V 1 μs 1.5 μs
±0.5 V 1.5 μs 2 μs
±0.1 V, ±0.2 V 2 μs 8 μs

Typical Performance Graphs

Figure 5. Settling Error versus Time for Different Source Impedances


Figure 6. AI Small Signal Bandwidth


Figure 7. AI CMRR


AI Absolute Accuracy

Note Accuracies listed are valid for up to two years from the device external calibration.
Table 10. AI Absolute Accuracy
Nominal Range Positive Full Scale Nominal Range Negative Full Scale Residual Gain Error (ppm of Reading) Residual Offset Error (ppm of Range) Offset Tempco (ppm of Range/°C) Random Noise, σ (μVrms) Absolute Accuracy at Full Scale (μV) Sensitivity (μV)
10 -10 60 20 21 280 1,920 112.0
5 -5 70 20 21 140 1,010 56.0
2 -2 70 20 24 57 410 22.8
1 -1 80 20 27 32 220 12.8
0.5 -0.5 90 40 34 21 130 8.4
0.2 -0.2 130 80 55 16 74 6.4
0.1 -0.1 150 150 90 15 52 6.0
Note Sensitivity is the smallest voltage change that can be detected. It is a function of noise.
Table 11. AI Absolute Accuracy Values
Gain tempco 13 ppm/°C
Reference tempco 1 ppm/°C
INL error 60 ppm of range

AI Absolute Accuracy Equation

AbsoluteAccuracy = Reading · (GainError) + Range · (OffsetError) + NoiseUncertainty

  • GainError = ResidualAIGainError + GainTempco · (TempChangeFromLastInternalCal) + ReferenceTempco · (TempChangeFromLastExternalCal)
  • OffsetError = ResidualAIOffsetError + OffsetTempco · (TempChangeFromLastInternalCal) + INLError
  • NoiseUncertainty =
    RandomNoise3100
    for a coverage factor of 3 σ and averaging 100 points.

AI Absolute Accuracy Example

Absolute accuracy at full scale on the analog input channels is determined using the following assumptions:

  • TempChangeFromLastExternalCal = 10 °C
  • TempChangeFromLastInternalCal = 1 °C
  • number_of_readings = 100
  • CoverageFactor = 3 σ

For example, on the 10 V range, the absolute accuracy at full scale is as follows:

  • GainError = 60 ppm + 13 ppm · 1 + 1 ppm · 10 = 83 ppm
  • OffsetError = 20 ppm + 21 ppm · 1 + 60 ppm = 101 ppm
  • NoiseUncertainty =
    280µV3100
    = 84 µV
  • AbsoluteAccuracy = 10 V · (GainError) + 10 V · (OffsetError) + NoiseUncertainty = 1,920 µV

Analog Triggers

Table 12. Analog Triggers
Number of triggers 1
Source AI <0..15>, APFI 0
Functions Start Trigger, Reference Trigger, Pause Trigger, Sample Clock, Convert Clock, Sample Clock Timebase
Resolution 10 bits, 1 in 1,024
Modes Analog edge triggering, analog edge triggering with hysteresis, and analog window triggering
Accuracy ±1%
Table 13. Analog Trigger Source Level
AI <0..15> ±Full scale
APFI 0 ±10 V
Table 14. Analog Trigger Bandwidth (-3 dB)
AI <0..15> 3.4 MHz
APFI 0 3.9 MHz
Table 15. APFI 0
Input impedance 10 kΩ
Coupling DC
Protection, power on ±30 V
Protection, power off ±15 V

Analog Output

Table 16. Analog Output
Number of channels 2
DAC resolution 16 bits
DNL ±1 LSB
Monotonicity 16 bit guaranteed
Accuracy Refer to AO Absolute Accuracy
Timing accuracy 50 ppm of sample rate
Timing resolution 50 ns
Output range ±5 V, ±10 V, ±external reference on APFI 0
Output coupling DC
Output impedance 0.2 Ω
Output current drive ±5 mA
Overdrive protection ±25 V
Overdrive current 20 mA
Power-on state ±5 mV[1]1 When the USB Screw Terminal device is powered on, the analog output signal is not defined until after USB configuration is complete.
Power-on glitch 1.5 V peak for 1.5 s
Output FIFO size 8,191 samples shared among channels used
AO waveform modes Non-periodic waveform, periodic waveform regeneration mode from onboard FIFO, periodic waveform regeneration from host buffer including dynamic update
Settling time, full-scale step, 15 ppm (1 LSB) 2 µs
Slew rate 20 V/µs
Table 17. AO Maximum Update Rate
1 channel 2.86 MS/s
2 channels 2.00 MS/s per channel
Table 18. AO Data Transfers
PCI/PCI Express/PXI/PXI Express DMA (scatter-gather), interrupts, programmed I/O
USB USB Signal Stream, programmed I/O
Table 19. AO Glitch Energy at Midscale Transition, ±10 V Range
Magnitude 10 mV
Duration 1 µs

AO Absolute Accuracy

Absolute accuracy at full-scale numbers is valid immediately following internal calibration and assumes the device is operating within 10 °C of the last external calibration.

Note Accuracies listed are valid for up to two years from the device external calibration.
Table 20. AO Absolute Accuracy
Nominal Range Positive Full Scale Nominal Range Negative Full Scale Residual Gain Error (ppm of Reading) Gain Tempco (ppm/°C) Residual Offset Error (ppm of Range) Offset Tempco (ppm of Range/°C) Absolute Accuracy at Full Scale (μV)
10 -10 75 17 40 2 2,080
5 -5 85 8 40 2 1,045
Table 21. AO Absolute Accuracy Values
Reference tempco 1 ppm/°C
INL error 64 ppm of range

AO Absolute Accuracy Equation

AbsoluteAccuracy = OutputValue · (GainError) + Range · (OffsetError)

  • GainError = ResidualGainError + GainTempco · (TempChangeFromLastInternalCal) + ReferenceTempco · (TempChangeFromLastExternalCal)
  • OffsetError = ResidualOffsetError + AOOffsetTempco · (TempChangeFromLastInternalCal) + INLError

External Reference

Table 22. APFI 0
Input impedance 10 kΩ
Coupling DC
Protection, power on ±30 V
Protection, power off ±15 V
Range ± 11 V
Slew rate 20 V/μs
Figure 8. AO External Reference Bandwidth


Digital I/O/PFI

Static Characteristics

Table 23. Static DIO/PFI Characteristics
Number of channels 24 total, 8 (P0.<0..7>), 16 (PFI <0..7>/P1, PFI <8..15>/P2)
Ground reference D GND
Direction control Each terminal individually programmable as input or output
Pull-down resistor 50 kΩ typical, 20 kΩ minimum
Input voltage protection ±20 V on up to two pins[2]2 Stresses beyond those listed under Input voltage protection may cause permanent damage to the device.

Waveform Characteristics (Port 0 Only)

Table 24. DIO Waveform Characteristics (Port 0 Only)
Terminals used Port 0 (P0.<0..7>)
Port/sample size Up to 8 bits
Waveform generation (DO) FIFO 2,047 samples
Waveform acquisition (DI) FIFO 2,047 samples
DI or DO Sample Clock source[3]3 The digital subsystem does not have its own dedicated internal timing engine. Therefore, a sample clock must be provided from another subsystem on the device or an external source. Any PFI, RTSI, AI Sample or Convert Clock, AO Sample Clock, Ctr n Internal Output, and many other signals
Table 25. DI Sample Clock Frequency
PCI/PCI Express/PXI/PXI Express 0 MHz to 10 MHz, system and bus activity dependent
USB 0 MHz to 1 MHz, system and bus activity dependent
Table 26. DO Sample Clock Frequency (PCI/PCI Express/PXI/PXI Express)
Regenerate from FIFO 0 MHz to 10 MHz
Streaming from memory 0 to 10 MHz, system and bus activity dependent
Table 27. DO Sample Clock Frequency (USB)
Regenerate from FIFO 0 MHz to 10 MHz
Streaming from memory 0 MHz to 1 MHz, system and bus activity dependent
Table 28. Data Transfers
PCI/PCI Express/PXI/PXI Express DMA (scatter-gather), interrupts, programmed I/O
USB USB Signal Stream, programmed I/O

PFI/Port 1/Port 2 Functionality

Table 29. PFI/Port 1/Port 2 Functionality
Functionality Static digital input, static digital output, timing input, timing output
Timing output sources Many AI, AO, counter, DI, DO timing signals
Debounce filter settings 125 ns, 6.425 µs, 2.56 ms, disable; high and low transitions; selectable per input

Recommended Operating Conditions

Table 30. Recommended Operating Conditions
Level Minimum Maximum
Input high voltage (VIH) 2.2 V 5.25 V
Input low voltage (VIL) 0 V 0.8 V
Output high current (IOH) P0.<0..7> -24 mA
Output high current (IOH) PFI <0..15>/P1/P2 -16 mA
Output low current (IOL) P0.<0..7> 24 mA
Output low current (IOL) PFI <0..15>/P1/P2 16 mA

Electrical Characteristics

Table 31. Electrical Characteristics
Level Minimum Maximum
Positive-going threshold (VT+) 2.2 V
Negative-going threshold (VT-) 0.8 V
Delta VT hysteresis (VT+ - VT-) 0.2 V
IIL input low current (Vin = 0 V) -10 µA
IIH input high current (Vin = 5 V) 250 µA

Digital I/O Characteristics

Figure 9. P0.<0..7>: Ioh versus Voh


Figure 10. PFI <0..15>/P1/P2: Ioh versus Voh


Figure 11. P0.<0..7>: Iol versus Vol


Figure 12. PFI <0..15>/P1/P2: Iol versus Vol


General-Purpose Counters/Timers

Table 32. General-Purpose Counters/Timers
Number of counter/timers 2
Resolution 32 bits
Counter measurements Edge counting, pulse, semi-period, period, two-edge separation
Position measurements X1, X2, X4 quadrature encoding with Channel Z reloading; two-pulse encoding
Output applications Pulse, pulse train with dynamic updates, frequency division, equivalent time sampling
Internal base clocks 80 MHz, 20 MHz, 0.1 MHz
External base clock frequency 0 MHz to 20 MHz
Base clock accuracy 50 ppm
Inputs Gate, Source, HW_Arm, Aux, A, B, Z, Up_Down
Routing options for inputs Any PFI, RTSI, PXI_TRIG, PXI_STAR, analog trigger, many internal signals
FIFO 2 samples
Table 33. Data Transfers
PCI/PCI Express/PXI/PXI Express Dedicated scatter-gather DMA controller for each counter/timer; interrupts, programmed I/O
USB USB Signal Stream, programmed I/O

Frequency Generator

Table 34. Frequency Generator
Number of channels 1
Base clocks 10 MHz, 100 kHz
Divisors 1 to 16
Base clock accuracy 50 ppm

Output can be available on any output PFI or RTSI terminal.

Phase-Locked Loop (PLL) (PCI/PCI Express/PXI/PXI Express Only)

Table 35. PLL
Number of PLLs 1
Reference signal PXI_STAR, PXI_CLK10, RTSI <0..7>
Output of PLL 80 MHz Timebase; other signals derived from 80 MHz Timebase including 20 MHz and 100 kHz Timebases

External Digital Triggers

Table 36. External Digital Triggers
Source Any PFI, RTSI, PXI_TRIG, PXI_STAR
Polarity Software-selectable for most signals
Analog input function Start Trigger, Reference Trigger, Pause Trigger, Sample Clock, Convert Clock, Sample Clock Timebase
Analog output function Start Trigger, Pause Trigger, Sample Clock, Sample Clock Timebase
Counter/timer function Gate, Source, HW_Arm, Aux, A, B, Z, Up_Down
Digital waveform generation (DO) function Sample Clock
Digital waveform acquisition (DI) function Sample Clock

Device-to-Device Trigger Bus

Table 37. Device-to-Device Trigger Bus Characteristics
PCI/PCI Express RTSI <0..7>[4]4 In other sections of this document, RTSI refers to RTSI <0..7> for the PCI/PCI Express devices or PXI_TRIG <0..7> for PXI/PXI Express devices.
PXI/PXI Express PXI_TRIG <0..7>, PXI_STAR
USB source None
Output selections 10 MHz Clock, frequency generator output, many internal signals
Debounce filter settings 125 ns, 6.425 μs, 2.56 ms, disable; high and low transitions; selectable per input

Bus Interface

Table 38. PCI/PXI Bus Interface
PCI/PXI 3.3 V or 5 V signal environment
DMA channels 6, can be used for analog input, analog output, digital input, digital output, counter/timer 0, counter/timer 1
Table 39. PCI Express Bus Interface
Form factor x1 PCI Express, specification v1.0a compliant
Slot compatibility x1, x4, x8, and x16 PCI Express slots[5]5 Some motherboards reserve the x16 for graphics use. For PCI Express guidelines, refer to ni.com/pciexpress.
DMA channels 6, can be used for analog input, analog output, digital input, digital output, counter/timer 0, counter/timer 1
Table 40. PXI Express Bus Interface
Form factor x1 PXI Express peripheral module, specification rev 1.0 compliant
Slot compatibility x1 and x4 PXI Express or PXI Express hybrid slots
DMA channels 6, can be used for analog input, analog output, digital input, digital output, counter/timer 0, counter/timer 1
Table 41. USB Bus Interface
USB USB 2.0 Hi-Speed or full-speed[6]6 If you are using an USB M Series device in full-speed mode, device performance will be lower and you will not be able to achieve maximum sample/update rates., [7]7 Operating on a full-speed bus may result in lower performance.
USB Signal Stream 4, can be used for analog input, analog output, digital input, digital output, counter/timer 0, counter/timer 1
The PXI device supports one of the following features:
  • May be installed in PXI Express hybrid slots
  • Or, may be used to control SCXI in PXI/SCXI combo chassis
Table 42. PXI/SCXI Combo and PXI Express Chassis Compatibility
M Series Part Number SCXI Control in PXI/SCXI Combo Chassis PXI Express Hybrid Slot Compatible
191325D-03/191325E-03L No Yes
191325D-13/191325E-13L Yes No
191325C-0x/191325B-0x Yes No

The PXI Express device can be installed in PXI Express slots or PXI Express hybrid slots.

Power Requirements

Table 43. PCI/PXI Current Draw from Bus During No-Load Condition (Does Not Include P0/PFI/P1/P2 and +5 V Terminals)
+5 V 0.03 A
+3.3 V 0.725 A
+12 V 0.35 A
Table 44. PCI Express Current Draw from Bus During No-Load Condition (Does Not Include P0/PFI/P1/P2 and +5 V Terminals)
+3.3 V 0.925 A
+12 V 0.35 A
Table 45. PXI Express Current Draw from Bus During No-Load Condition (Does Not Include P0/PFI/P1/P2 and +5 V Terminals)
+3.3 V 0.45 A
+12 V 0.5 A
Table 46. PCI/PXI Current Draw from Bus During AI and AO Overvoltage Condition (Does Not Include P0/PFI/P1/P2 and +5 V Terminals)
+5 V 0.03 A
+3.3 V 1.2 A
+12 V 0.38 A
Table 47. PCI Express Current Draw from Bus During AI and AO Overvoltage Condition (Does Not Include P0/PFI/P1/P2 and +5 V Terminals)
+3.3 V 1.4 A
+12 V 0.38 A
Table 48. PXI Express Current Draw from Bus During AI and AO Overvoltage Condition (Does Not Include P0/PFI/P1/P2 and +5 V Terminals)
+3.3 V 0.48 A
+12 V 0.71 A
Caution USB devices must be powered with an NI offered AC adapter or a National Electric Code (NEC) Class 2 DC source that meets the power requirements for the device and has appropriate safety certification marks for country of use.
Table 49. USB Power Supply Requirements
USB power supply requirements 11 VDC to 30 VDC, 20 W, locking or non-locking power jack with 0.080 in. diameter center pin, 5/16-32 thread for locking collars

Current Limits

Caution Exceeding the current limits may cause unpredictable behavior by the device and/or PC/chassis.
Table 50. PCI Current Limits
+5 V terminal 1 A maximum. See note.
Note Older revisions of the PCI device have a self-resetting fuse that opens when current exceeds the current limit on the +5 V terminal. Newer revisions of the device have a traditional fuse that opens when current exceeds this specification. This fuse is not customer-replaceable; if the fuse permanently opens, return the device to NI for repair.
Table 51. PCI Express Current Limits (Without Disk Drive Power Connector Installed)
+5 V terminals combined 0.35 A maximum. See note.
P0/PFI/P1/P2 and +5 V terminals combined 0.39 A maximum
Note Older revisions of the PCI device have a self-resetting fuse that opens when current exceeds the current limit on the +5 V terminal. Newer revisions of the device have a traditional fuse that opens when current exceeds this specification. This fuse is not customer-replaceable; if the fuse permanently opens, return the device to NI for repair.
Table 52. PCI Express Current Limits (With Disk Drive Power Connector Installed)
+5 V terminal 1 A maximum. See note.
P0/PFI/P1/P2 combined 0.39 A maximum
Note Older revisions of the PCI device have a self-resetting fuse that opens when current exceeds the current limit on the +5 V terminal. Newer revisions of the device have a traditional fuse that opens when current exceeds this specification. This fuse is not customer-replaceable; if the fuse permanently opens, return the device to NI for repair.
Table 53. PXI/PXI Express Current Limits
+5 V terminal 1 A maximum. See note.
P0/PFI/P1/P2 and +5 V terminals combined 2 A maximum
Note Older revisions of the PCI device have a self-resetting fuse that opens when current exceeds the current limit on the +5 V terminal. Newer revisions of the device have a traditional fuse that opens when current exceeds this specification. This fuse is not customer-replaceable; if the fuse permanently opens, return the device to NI for repair.
Table 54. USB Current Limits
+5 V terminal 1 A maximum. See note.
P0/PFI/P1/P2 and +5 V terminals combined 2 A maximum
Power supply fuse 2 A, 250 V

Physical Characteristics

Table 55. Dimensions
PCI printed circuit board 10.6 cm × 15.5 cm (4.2 in. × 6.1 in.)

For more information, visit ni.com/dimensions and search by module number.

PCI Express printed circuit board 10.0 cm × 16.9 cm (3.9 in. × 6.6 in) (half-length)
PXI/PXI Express printed circuit board Standard 3U PXI

For more information, visit ni.com/dimensions and search by module number.

USB Screw Terminal (includes connectors) 26.67 cm × 17.09 cm × 4.45 cm(10.5 in. × 6.73 in. × 1.75 in.)
USB BNC (includes connectors) 28.6 cm × 17 cm × 6.9 cm(11.25 in. × 6.7 in. × 2.7 in.)
USB Mass Termination enclosure (includes connectors) 18.8 cm × 17.09 cm × 4.45 cm (7.4 in. × 6.73 in. × 1.75 in.)
USB OEM Refer to the NI USB-622x/625x/628x OEM User Guide
Table 56. Weight
PCI 149 g (5.2 oz)
PCI Express 161 g (5.7 oz)
PXI 222 g (7.8 oz)
PXI Express 208 g (7.3 oz)
USB Screw Terminal 1.2 kg (2 lb 10 oz)
USB Mass Termination 816 g (1 lb 12.8 oz)
USB OEM 140 g (4.9 oz)
Table 57. I/O Connectors
PCI/PCI Express/ PXI/PXI Express 1 68-pin VHDCI
USB Screw Terminal 64 screw terminals
USB BNC 21 BNCs and 30 screw terminals
Mass Termination 1 68-pin SCSI
Table 58. PCI Express Disk Drive Power
PCI Express disk drive power Standard ATX peripheral connector (not serial ATA)
Table 59. Screw Terminal Wiring
USB/BNC 16 AWG to 28 AWG

Calibration

Table 60. Calibration
PCI/PXI/PCI Express/PXI Express recommended warm-up time 15 minutes
USB recommended warm-up time 30 minutes
Calibration interval 2 years

Maximum Working Voltage

Connect only voltages that are below these limits.

Table 61. Maximum Working Voltage
Channel-to-earth 11 V, Measurement Category I

Measurement Category I is for measurements performed on circuits not directly connected to the electrical distribution system referred to as MAINS voltage. MAINS is a hazardous live electrical supply system that powers equipment. This category is for measurements of voltages from specially protected secondary circuits. Such voltage measurements include signal levels, special equipment, limited-energy parts of equipment, circuits powered by regulated low-voltage sources, and electronics.

Caution Do not use for measurements within Categories II, III, or IV.
Note Measurement Categories CAT I and CAT O (Other) are equivalent. These test and measurement circuits are not intended for direct connection to the MAINS building installations of Measurement Categories CAT II, CAT III, or CAT IV.

Environmental

Table 62. Environmental Characteristics
PCI/PXI/PXI Express operating temperature 0 ºC to 55 ºC
PCI Express operating temperature 0 ºC to 50 ºC
USB operating temperature 0 ºC to 45 ºC
Storage temperature -20 ºC to 70 ºC
Humidity 10% RH to 90% RH, noncondensing
Maximum altitude 2,000 m
Pollution Degree 2
Indoor use only.

Shock and Vibration (PXI and PXI Express Only)

Table 63. Shock and Vibration
Operational shock 30 g peak, half-sine, 11 ms pulse (Tested in accordance with IEC 60068-2-27. Test profile developed in accordance with MIL-PRF-28800F.)
Random vibration, operating 5 Hz to 500 Hz, 0.3 grms
Random vibration, nonoperating 5 Hz to 500 Hz, 2.4 grms (Tested in accordance with IEC 60068-2-64. Nonoperating test profile exceeds the requirements of MIL-PRF-28800F, Class 3.)

Safety Compliance Standards

This product is designed to meet the requirements of the following electrical equipment safety standards for measurement, control, and laboratory use:

  • IEC 61010-1, EN 61010-1
  • UL 61010-1, CSA C22.2 No. 61010-1
Note For safety certifications, refer to the product label or the Product Certifications and Declarations section.

Electromagnetic Compatibility

This product meets the requirements of the following EMC standards for electrical equipment for measurement, control, and laboratory use:

  • EN 61326-1 (IEC 61326-1): Class A emissions; Basic immunity
  • EN 55011 (CISPR 11): Group 1, Class A emissions
  • AS/NZS CISPR 11: Group 1, Class A emissions
  • FCC 47 CFR Part 15B: Class A emissions
  • ICES-001: Class A emissions
Note In the United States (per FCC 47 CFR), Class A equipment is intended for use in commercial, light-industrial, and heavy-industrial locations. In Europe, Canada, Australia, and New Zealand (per CISPR 11) Class A equipment is intended for use only in heavy-industrial locations.
Note Group 1 equipment (per CISPR 11) is any industrial, scientific, or medical equipment that does not intentionally generate radio frequency energy for the treatment of material or inspection/analysis purposes.
Note For EMC declarations and certifications, refer to the Online Product Certification section.

Product Certifications and Declarations

Refer to the product Declaration of Conformity (DoC) for additional regulatory compliance information. To obtain product certifications and the DoC for NI products, visit ni.com/product-certifications, search by model number, and click the appropriate link.

1 When the USB Screw Terminal device is powered on, the analog output signal is not defined until after USB configuration is complete.

2 Stresses beyond those listed under Input voltage protection may cause permanent damage to the device.

3 The digital subsystem does not have its own dedicated internal timing engine. Therefore, a sample clock must be provided from another subsystem on the device or an external source.

4 In other sections of this document, RTSI refers to RTSI <0..7> for the PCI/PCI Express devices or PXI_TRIG <0..7> for PXI/PXI Express devices.

5 Some motherboards reserve the x16 for graphics use. For PCI Express guidelines, refer to ni.com/pciexpress.

6 If you are using an USB M Series device in full-speed mode, device performance will be lower and you will not be able to achieve maximum sample/update rates.

7 Operating on a full-speed bus may result in lower performance.