DAQ_Digital Pulse Generation Library VIs initialize, configure, generate, and close user-configurable terminals using counters. This library is applicable for digital I/O channels and modules that support timing output signals with PFI channels or other connections.

Note The supported frequency range for clock generation depends on the available Counter Timebase. The timebases available in X Series DAQ devices are 100 MHz, 20 MHz, and 100 kHz. The timebases available in TestScale devices are 80 MHz, 20 MHz, and 100 kHz. The counter timebase is selected based on the input configuration to generate a pulse at the required frequency.
  1. Use the DAQ_Digital Pulse Gen Initialize VI to initialize hardware and create a DAQmx Task for digital pulse generation.
  2. Specify the physical or global channel input to use for the counter. Only one counter can be used for a task. Use separate tasks for each counter if multiple counters are required.
  3. Provide the output terminal on which to generate the signal. Refer to the NI-DAQmx Device Terminals Help table. To access the table in NI MAX, select your device and right-click Device Pinout. Use the table to view the default PFI terminals of each counter for your device.
  4. If necessary, configure PFI lines.
    Note For the TestScale TS-15050 module only, P0.DIO<0:7> channels map to PFI<0:7> terminals. Refer to the TS-15050 Specifications for more information.
  5. Pass the digital pulse generation DAQmx Task to the DAQ_Digital Pulse Gen Configure and Measure VI.
  6. Configure the DAQ_Digital Pulse Gen Configure and Measure VI.
    • High time (s)—Specifies the high time of the pulse.
    • Low time (s)—Specifies the low time of the pulse.
    • Number of Pulses—Specifies the number of pulses to generate.
    • Actual Pulse Settings—Returns the actual high time, low time and generation time of the generated digital signal.
  7. Wire the updated digital pulse generation task from DAQmx Task Out.
  8. Close the digital pulse generation task using DAQ_Digital Pulse Gen Close VI.
Figure 33. Connection Block Diagram