NIWLANA_RESULT_DSSS_DEMOD_SAMPLE_CLOCK_OFFSET_MAXIMUM
- Updated2023-02-21
- 1 minute(s) read
| Data Type: | float64 |
| Access: | read only |
| Functions: | niWLANA_GetScalarAttributeF64 |
| Description: | Returns the maximum of sample clock offset estimates across iterations. This value is expressed in parts per million (ppm). The sample clock offset is the difference between the sample clocks at the digital-to-analog converter (DAC) of the transmitting device under test (DUT) and the digitizer. If the clock offset is more than 25 ppm, the estimated value may be inaccurate. Use the estimated offset to verify whether the DUT corresponds to section 18.4.7.5 of IEEE Standard 802.11b-1999 and section 20.3.21.6 of IEEE Standard 802.11n-2009. Note: If the magnitude of the carrier or the Sample clock frequency offset is greater than 25 ppm, I/Q gain imbalance magnitude is greater than 3 dB, and quadrature skew magnitude is greater than 15 degrees, the estimates of these impairments may be inaccurate. |