Time Overview

Use this instrument design library (IDL) to coordinate and manage time on USRP RIO devices. Time in the FPGA allows you to register events at a future time on the device. Future time events can be used to implement timed Start Triggers, or other timed commands.

Topology for Time

The Time IDL creates a common periodic time reference (CPTR) from the Reference Clock and a pulse-per-second (PPS) signal. Each device must be locked to the same Reference Clock and must use the same PPS. If you are using a single device, you can use the internal Reference Clock and internal PPS of the device. If you are using multiple devices, NI recommends a CDA-2990 Clock Distribution Device for the common Reference Clock and PPS. You can connect the 10 MHz OUT of the CDA-2990 to the REF IN of the USRP RIO devices, and connect the PPS OUT of the CDA-2990 to the PPS TRIG IN of the USRP RIO devices.

Caveats and Requirements

  • The Time IDL does not account for differences in analog signal paths.
  • The Time IDL does not account for data pipeline delays that occur before and after the Time VIs. For example, Time does not account for ADC/DAC pipeline delays.
  • You must lock all devices to a common Reference Clock.
  • The Time IDL does not account for propagation delays of the Reference Clock.
  • The Time IDL generates the CPTR from the Reference Clock and the PPS. You must guarantee that a PPS edge will always select the same edge of the Reference Clock across all devices.

Using Time

The Time IDL contains both host and FPGA VIs that must be present.

FPGA

The FPGA requires three VIs to manage time:

  • The Create Time VI lives outside all loops and creates the LabVIEW FPGA resources used by the Time IDL on the FPGA.
  • The Time Register Bus VI connects to the Register Bus in the 40 MHz clock domain and enables communication between the FPGA and the host.
  • The Timekeeper VI runs the time process where time is maintained and set.

Host

On the host side, wire Initialize.vi and then Set Time.vi. The devices now have the specified time in their FPGA.

Using Future Events

Future events contain both host and FPGA VIs that must be present.

FPGA

The FPGA requires at least three VIs to manage future events:

  • The Create Future Event VI lives outside all loops and creates the LabVIEW FPGA resources used by the future event instance on the FPGA.
  • The Future Event Register Bus VI connects to the Register Bus in the 40 MHz clock domain and enables communication between the FPGA and the host for the future events.
  • The Future Event VI runs the process, or where the future event occurs, of the future event.
Note Because each future event instance stores only a single future event, multiple future event instances are supported. Each future event instance must have its own set of resources from the Create Future Event VI and its own future event process from the Future Event VI.
Note Place the future event process in the same single-cycle timed loop (SCTL) as the time process to minimize the jitter in the time of the future event.

Host

After you set the time on the host, wire Set Future Event.vi with a future time for a specific future event instance.