Use the phase-locked loop (PLL) circuit on an NI-Sync device to synchronize your system timing module's oscillator to an external reference clock. Once the oscillator is synchronized, you can route it to the backplane using the PXI_Clk10_In connector, which can then phase lock the PXI_Clk10 and PXIe_Clk100 signals to the oscillator. Using a PLL circuit, you can perform the following actions:

  • Align the frequency of your system timing module's oscillator with an external clock.
  • Lock PXI_Clk10 and PXIe_Clk100 to the same external reference clock.
  • Phase-lock PXI_Clk10 to a higher frequency clock.
  • Lock multiple boards to a shared reference signal that is not interrupted even if the external reference clock is disconnected.