NIRFSG_ATTR_SYNC_SAMPLE_CLOCK_MASTER
- Updated2024-05-08
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NIRFSG_ATTR_SYNC_SAMPLE_CLOCK_MASTER
| Data type |
Access | Coercion | High Level Functions |
|---|---|---|---|
| ViBoolean | R/W | None | None |
Description
Specifies whether the device is the master device when synchronizing the Sample Clock between multiple devices. The master device distributes the Sample Clock sync signal to all devices in the system through the Sample Clock sync distribution line.
When synchronizing the Sample Clock, one device must always be designated as the master. The master device actively drives the Sample Clock sync distribution line.
To set this attribute, the NI-RFSG device must be in the Configuration state.
Defined Values:
| VI_TRUE | The device is the master device for synchronizing the Sample Clock. |
| VI_FALSE | The device is not the master for synchronizing the Sample Clock. |
Default Value: VI_FALSE
Supported Devices: PXIe-5646
Related Topics
Synchronization Using NI-RFSA and NI-RFSG—Refer to this topic for more information about PXIe-5646 device synchronization.