PXIe-5840 FPGA I/O Resources

The following tables describe LabVIEW FPGA I/O resources visible in the LabVIEW project.

RF IN

FPGA I/O Resource Name Description Data Type Required Clock Domain
RF In 0/I This resource is the I data that comes from the RF IN 0 connector. Array of eight fixed-point numbers1<±, 14, 1>2 Data Clock
RF In 0/Q This resource is the Q data that comes from the RF IN 0 connector. Array of eight fixed-point numbers1<±, 14, 1>2 Data Clock
RF In 0/I Overrange Returns TRUE when the RF input subsystem tries to acquire a signal that is larger in amplitude than the ADC can accurately measure using the current hardware gain configuration. This problem can be caused by using a reference level that is too low for the supplied input signal. Array of eight Boolean values1 Data Clock
RF In 0/Q Overrange Returns TRUE when the RF input subsystem tries to acquire a signal that is larger in amplitude than the ADC can accurately measure using the current hardware gain configuration. This problem can be caused by using a reference level that is too low for the supplied input signal. Array of eight Boolean values1 Data Clock

1The sample at index 0 corresponds to the first sample read from the ADC, while the sample at index 1 corresponds to the second sample read from the ADC, while the sample at index 1 corresponds to the second sample read from the ADC, and so on.

2The <±, 14, 1> notation corresponds to a signed, fixed-point number with a 14-bit word length and a 1-bit integer word length.

RF OUT

FPGA I/O Resource Name Description Data Type Required Clock Domain
RF Out 0/I This resource is the I data that goes to the RF OUT 0 connector. Array of eight fixed-point numbers1<±, 16, 1>2 Data Clock
RF Out 0/Q This resource is the Q data that goes to the RF OUT 0 connector. Array of eight fixed-point numbers1<±, 16, 1>2 Data Clock

1The sample at index 0 corresponds to the first sample read from the DAC, while the sample at index 1 corresponds to the second sample written to the DAC, and so on.

2The <±, 16, 1> notation corresponds to a signed, fixed-point number with a 16-bit word length and a 1-bit integer word length.

Module Status

FPGA I/O Resource Name Description Data Type Required Clock Domain
Data Clock Locked Returns TRUE when the Sample Clock and Data Clock PLLs are currently locked. . Boolean Any
RF In 0 LO Locked Returns TRUE when the local oscillator of the RF input subsystem is currently locked to the specified frequency. Boolean Any
RF Out 0 LO Locked Returns TRUE when the local oscillator of the RF output subsystem is currently locked to the specified frequency. Boolean Any
RF In 0 Valid Returns TRUE when the RF input subsystem is ready for operation. Boolean Any
RF Out 0 Ready Returns TRUE when the RF output subsystem is ready for operation. Boolean Any
DRAM Bank 0 Ready Indicates that DRAM Bank 0 has completed initialization and is ready to be accessed. This signal is FALSE when the FPGA first starts running. Boolean Any
DRAM Bank 1 Ready Indicates that DRAM Bank 1 has completed initialization and is ready to be accessed. This signal is FALSE when the FPGA first starts running. Boolean Any
FPGA Temperature Error Returns TRUE when the module has exceeded its safe operating temperature range. If this condition occurs, shut down the chassis and check for proper cooling. Boolean Any
FPGA Voltage or Power Error Returns TRUE when the module has exceeded its safe operating current or power draw from the backplane. Boolean Any

PXI

FPGA I/O Resource Name Description Data Type Required Clock Domain
PXI_TrigX Controls PXI trigger line X, where X is a PXI trigger line number between 0 and 7. Use an FPGA I/O node configured for reading or writing, or use the Set Output Data or Set Output Enable methods to access this digital I/O line. Follow the guidelines for using PXI triggers with the LabVIEW FPGA Module for proper module and PXI system functionality. Boolean Any
PXI_TrigX Ready Returns FALSE when the associated PXI_TrigX line is requested to change direction. Returns TRUE once the direction change is complete. Boolean Any
PXI_Star Controls PXI_Star line. Use an FPGA I/O node configured for reading or writing, or use the Set Output Data or Set Output Enable methods to access this digital I/O line. Follow the guidelines for using PXI triggers with the LabVIEW FPGA Module for proper module and PXI system functionality. Boolean Any
PXI_Star Ready Returns FALSE when the associated PXI_Star Ready line is requested to change direction. Returns TRUE once the direction change is complete. Boolean Any
PXIe_DStarA Provides access to the PXIe_DStarA trigger line. Use an FPGA I/O node configured for reading to access this digital input line. Boolean Any
PXIe_DStarB Provides access to the PXIe_DStarB trigger line. Use an FPGA I/O node configured for reading to access this digital input line. Boolean Any
PXIe_DStarC Provides access to the PXIe_DStarC trigger line. Use an FPGA I/O node configured for writing to access this digital output line. Boolean Any
PXIe_Sync100 This signal is TRUE for each cycle of PXIe_CLK100 that corresponds to a rising edge of PXI_CLK10. Boolean PXIe_CLK100

DIO

FPGA I/O Resource Name Description Data Type Required Clock Domain
DIO X Controls digital I/O line X, where X is a digital I/O line number between 0 and 7. Use an FPGA I/O node configured for reading, or use the Set Output Data or Set Output Enable methods to access this digital I/O line Boolean Any
DIO Ready X Returns FALSE when the associated DIO line is requested to change direction. Returns TRUE once the direction change is complete. Boolean Any
DIO Voltage Controls the voltage high level of the LVCMOS DIO channels. 1.2 V=255, 1.5 V=207, 1.8 V=173, 2.5 V=124, 3.3 V=94. Byte Integer (U8) Any
DIO Voltage Ready Returns TRUE when the DIO Voltage has been set to the requested value and is ready for operation. Boolean Any
DIO 5V Enable Controls the 5 V power supply on the Molex Nano-Pitch I/O Connector. Boolean Any
DIO 5V Ready Returns TRUE when the DIO 5 V has been enabled and is ready for operation Boolean Any

Other

FPGA I/O Resource Name Description Data Type Required Clock Domain
Active LED Controls the Active LED on the front panel of the module. An enumerated type with values Off, Green, Red, and Amber. Any
PFI 0 Input Data X Four inputs connected with the PFI 0 front panel connector of the module, where X is A, B, C, or D. Use an FPGA I/O node configured for reading to access each of these digital I/O lines. Boolean Any
PFI 0 Output Data This signal is connected with the PFI 0 front panel connector of the module. Use an FPGA I/O node configured for writing to set the value output on this digital I/O line. Boolean Any
PFI 0 Output Enable This signal controls whether the PFI 0 front panel connector is configured as a input or output. Use an FPGA I/O node configured for writing to set the output enable of this digital I/O line. Boolean Any
RF Out 0 Blanking Setting this value to TRUE puts the RF output subsystem into a very low output power state.

Setting this value to FALSE returns the RF output subsystem to its previously configured setting.

Boolean Any