Adjust Sample Clock Relative Delay

Adjust Sample Clock Relative Delay

Delays (or phase shifts) the Sample Clock, which delays the output of the waveform generator.

The delay takes effect immediately after this node is called. Delaying the Sample Clock can be useful when lining up the output of multiple instruments or when intentionally phase shifting the output relative to a fixed reference, such as the PLL Reference Clock.

Inputs/Outputs

session in

Handle that identifies your instrument session previously allocated by Initialize With Channels.

error in

Error conditions that occur before this node runs.

The node responds to this input according to standard error behavior.

Standard Error Behavior

Default value: No error

adjustment time

Amount of time to adjust the Sample Clock delay in seconds (s).

adjustment time can be positive or negative, but it must be less than or equal to the Sample Clock period.

session out

Reference to your instrument session to wire to the next node.

error out

Error information.

The node produces this output according to standard error behavior.

Standard Error Behavior

Programming Patterns

Calling this node after calling NI-TClk Synchronize breaks synchronization.

Delaying an External Sample Clock

To delay an external Sample Clock, set the Sample Clock Absolute Delay property.