Digital Input Express VI
- Updated2023-02-21
- 4 minute(s) read
Requires: myRIO, roboRIO, ELVIS RIO Control, or ELVIS III Toolkit
Reads values from one or more digital input channels.
This Express VI reads one sample each time with the default FPGA personality. This Express VI reads one sample or multiple samples each time with the high-throughput FPGA personality. Visit ni.com/info and enter the Info Code ex6g5a to learn about the myRIO high-throughput FPGA personality. Visit ni.com/info and enter the Info Code exqmja to learn about the NI ELVIS RIO CM high-throughput FPGA personality.
This Express VI reads one sample each time with the default FPGA personality on the roboRIO. The roboRIO uses a 5 V voltage rail on the DIO port for powering sensors and provides 3.3 V DIO lines for generating digital input signals.
This Express VI reads one sample or multiple samples each time.
| Dialog Box Options |
| Block Diagram Inputs |
| Block Diagram Outputs |
Dialog Box Options
| Parameter | Description |
|---|---|
| I/O mode | Specifies whether the hardware acquires one sample or multiple samples each time for a channel. The default is Digital input (1 sample). This option is available only when you use the FPGA personality that supports multiple I/O modes. |
| Node name | Specifies the name of this Express VI. You can also double-click the name of this Express VI on the expandable node to edit the name. |
| Channel | Specifies the digital input channel from which to read the value. If the channel you select is set as a digital output channel, this Express VI changes the channel to a digital input channel before reading the value. |
| Custom channel name | Specifies a custom name for the digital input channel that you select. |
| Remove channel | Deletes the digital input channel that you select. This option is available only when you select multiple channels. |
| Add channel | Adds a new digital input channel to the channel list. You can add up to 12 digital input channels. You can add up to 40 digital input channels. Two Digital Input Express VIs will block each other when they access channels from the same bank, given that both VIs are in n samples mode. |
| Sample rate | Specifies the sampling frequency of the input signal. If you specify a frequency that is invalid, this Express VI coerces the specified value to the nearest valid value when you click Validate. This option is available only when you specify Digital input (n samples) for I/O mode.
|
| Samples | Specifies the number of samples to read. The default is 1,000. Valid values must be greater than 0 and less than or equal to 10,000. This option is available only when you specify Digital input (n samples) for I/O mode. |
| Latency | Displays the latency between two adjacent signal acquisition iterations. Refer to the Details section of this topic for more information about latency. This option is available only when you specify Digital input (n samples) for I/O mode. |
| View Code | Displays the underlying code of this Express VI. |
| Connection Diagram | Shows the I/O connector pinouts. The highlighted pinouts represent the channels that you configure. |
Block Diagram Inputs
| Parameter | Description |
|---|---|
| error in (no error) | Describes error conditions that occur before this node runs. |
Block Diagram Outputs
| Parameter | Description |
|---|---|
| Channel name | Returns the value that this Express VI reads from the digital input channel that you select, where channel name is the name of the digital input channel. |
| error out | Contains error information. This output provides standard error out functionality. |
Digital Input Details
The following figure demonstrates the latency when you use the Digital Input Express VI to perform n samples read operations. You need to choose an FPGA personality that supports n samples I/O mode to perform n samples read operations.
In the previous figure, the x-axis represents time and the y-axis represents amplitude. The waveform in blue represents the signal that the hardware acquires. The red dotted line represents latency. When latency occurs, the hardware does not acquire any signal. In other words, the time interval between two adjacent signal acquisition iterations is latency.
 | Note For any application that uses one or more Express VIs, you must use the Reset VI at the end of the application to reset the FPGA target and all the I/O channels. Otherwise, the Express VIs might not execute correctly when you run the application for the second time. |
Related Information
1 Sample versus N Samples Modes (myRIO Toolkit)
1 Sample versus N Samples Modes (ELVIS RIO Control Toolkit)
1 Sample versus N Samples Modes (ELVIS III Toolkit)
Generating FPGA Clocks (myRIO Toolkit)
Generating FPGA Clocks (roboRIO Toolkit)
Generating FPGA Clocks (ELVIS RIO Control Toolkit)
Generating FPGA Clocks (ELVIS III Toolkit)
I/O Connectors (myRIO Toolkit)
I/O Connectors (roboRIO Toolkit)
I/O Connectors (ELVIS III Toolkit)