You can synchronize the NI 9470 with other modules that are connected to the same FPGA device if your application meets the following requirements:

  • The modules must use the same master timebase source
  • The modules must start acquisition mode at the same time
  • Each channel of the NI 9470 must be in its own FPGA I/O Node residing in its own loop.

Create FPGA I/O items for the module before you can configure the items using the FPGA I/O Node. Develop the FPGA VI to meet the guidelines described in the following table.

For delta-sigma modules, you will need to synchronize multiple sample rates.

Table 465. FPGA VI Development Guidelines
Guideline Details
Share a master timebase source Configure the modules to share master timebase source.
Start the synchronized acquisition
  • Configure an FPGA I/O Node with Start channels for the module you want to synchronize.
  • Wire a Boolean constant set to TRUE to each Start channel.
  • Ensure that all Start channels are in the same FPGA I/O Node. The data will not be synchronized if they are not.
Acquire data from synchronized modules
  • Create separate loops for each channel of the NI 9470 that runs at a different data rate. Channels that are configured to run at the same data rate can either be in the same loop or be in a separate loop.
  • For channels that are configured to run at different data rates, configure an FPGA I/O Node in each loop. For channels that are configured to run at the same data rate, you can either configure one FPGA I/O Node for the all the channels or configure an FPGA I/O Node for each channel. If you place channels that are configured for different data rates in the same loop, LabVIEW returns an overrun warning, error 65539, from the FPGA I/O Node for the AI channels and an underflow warning, error 65676, from the FPGA I/O Node for the AO channels.
  • A delay occurs before the FPGA I/O Node returns the first data point. The length of the delay depends on the data rate and the PWM Divisor for each NI 9470 channel.
  • Refer to Synchronizing Multiple Modules (FPGA Interface) for how to synchronize other DSA modules that are synchronized with the NI 9470.
Understand the maximum sample rate when synchronizing multiple modules —
Table 466. Equation for Synchronizing Multiple Sample Rates
12.8 MHz OCLK13.1072 MHz OCLKTime to First Channel Sample(s)
3.200 kS/s3.277 kS/s(14,472,838 + 4,000 * n) * (Master Timebase Period ± 1 Master Timebase Period)
3.125 kS/s3.200 kS/s(14,472,838 + 4,096 * n) * (Master Timebase Period ± 1 Master Timebase Period)
2.560 KS/s2.621 KS/s(14,472,838 + 5,000 * n) * (Master Timebase Period ± 1 Master Timebase Period)
2.000 KS/s2.048 KS/s(14,473,006 + 6,400 * n) * (Master Timebase Period ± 1 Master Timebase Period)
Note Master Timebase Period = period of the internal or external clock that the module uses (1/12.8 MHz or 1/13.072 MHz). n = channel PWN divisor. Refer to the PWM Divisor I/O Property for valid values of n for each data rate divisor option. Only data rates of 3.125 kS/s or 2.000 kS/s with 12.8 MHz OCLK or 3.200 kS/s or 2.048 kS/s with 13.1072 MHz OCLK are compatible with other DSA modules for synchronizing multiple modules. The formulas above apply to each individual channel of the NI 9470 based on each channel's PWM divisor.