Use an FPGA I/O Node configured for reading and writing with this device.

Use the FPGA I/O Node to access the following terminals for this device.

Table 634. Terminals in Software
Terminal Description
Conn0_AI/AIx Analog input channel x, where x is the number of the channel. The sbRIO-9629 has AI channels 0 to 15.
Conn0_AO/AOx Analog output channel x, where x is the number of the channel. The sbRIO-9629 has AO channels 0 to 3.
Conn0_DIO0-3/DIOx Digital input/output channel x, where x is the channel number. The sbRIO-9629 has DIO channels 0 to 3.
Conn0_DIO0-3/DIO3:0 Digital port consisting of channels 0 through 3. Channel 3 signifies the MSB and channel 0 signifies the LSB.

Arbitration

You cannot configure arbitration settings for analog input and analog output channels of this device. Analog input and analog output channels on this device only support the Arbitrate if Multiple Requestors Only option for arbitration.

Configure the arbitration settings for digital output channels on this device in the Advanced Code Generation page on the FPGA I/O Properties dialog box. The default arbitration setting is Never Arbitrate.

Digital input channels on this device only support the Never Arbitrate option for arbitration. You cannot configure arbitration settings for digital input channels on this device.

I/O Methods

Use the FPGA I/O Method Node to access the following I/O methods for this device.

Table 635. I/O Methods
Method I/O Type Description
Set Output Data DIO Refer to the FPGA I/O Method Node topic for a description of this method.
Set Output Enable DIO Sets the line direction of the digital channel or the digital port. Refer to the FPGA I/O Method Node topic for a description of this method.

Module Methods

Use the FPGA I/O Method Node to access the following I/O methods for this device.

Table 636. Module Methods
Method I/O Type Description
Check Status DIO Returns a Boolean value that indicates whether the DIO module is ready for I/O operations.

I/O Properties

Use the FPGA I/O Property Node to access the following properties for this device.

Table 637. I/O Properties
Property I/O Type Description
Terminal Mode AI Sets the terminal mode for a channel as RSE (referenced single-ended) or DIFF (differential). This property overwrites the value you configure in the Module Properties dialog box. You cannot configure channels 8 through 15 to DIFF mode.
Voltage Range AI Sets the input range for a channel as ±10 V, ±5 V, ±2 V, or ±1 V. This property overwrites the value you configure in the Module Properties dialog box.
LSB Weight AO Returns the LSB weight in nV/LSB for the channel. Use this value to convert AO data if you set the Calibration Mode to Raw in the Module Properties dialog box.
Offset AO Returns the calibration offset in nV for the channel. Use this value to convert AO data if you set the Calibration Mode to Raw in the Module Properties dialog box.

Module Properties

Use the FPGA I/O Property Node to access the following properties for this device.

Table 638. Module Properties
Property I/O Type Description
LSB Weight (±10 V range) AI Returns the LSB weight in pV/LSB for the ±10 V range. Use this value to convert AI data if you set the Calibration Mode to Raw in the Module Properties dialog box.
LSB Weight (±5 V range) AI Returns the LSB weight in pV/LSB for the ±5 V range. Use this value to convert AI data if you set the Calibration Mode to Raw in the Module Properties dialog box.
LSB Weight (±2 V range) AI Returns the LSB weight in pV/LSB for the ±2 V range. Use this value to convert AI data if you set the Calibration Mode to Raw in the Module Properties dialog box.
LSB Weight (±1 V range) AI Returns the LSB weight in pV/LSB for the ±1 V range. Use this value to convert AI data if you set the Calibration Mode to Raw in the Module Properties dialog box.
Offset (±10 V range) AI Returns the calibration offset in nV for the ±10 V range. Use this value to convert AI data if you set the Calibration Mode to Raw in the Module Properties dialog box.
Offset (±5 V range) AI Returns the calibration offset in nV for the ±5 V range. Use this value to convert AI data if you set the Calibration Mode to Raw in the Module Properties dialog box.
Offset (±2 V range) AI Returns the calibration offset in nV for the ±2 V range. Use this value to convert AI data if you set the Calibration Mode to Raw in the Module Properties dialog box.
Offset (±1 V range) AI Returns the calibration offset in nV for the ±1 V range. Use this value to convert AI data if you set the Calibration Mode to Raw in the Module Properties dialog box.

Single-Cycle Timed Loop

This device supports the single-cycle Timed Loop for digital I/O only. To configure the number of output synchronizing registers or input synchronizing registers for the channels on this device, use the Advanced Code Generation page of the FPGA I/O Properties dialog box

The Set Output Enable method node is not supported in the single-cycle Timed Loop. When writing to a DIO I/O node in a single-cycle Timed Loop, the I/O node will not change the DIO line directions. To set the line directions to output when writing to the DIO channels in a single-cycle Timed Loop, either configure the default line directions to output in the Module Properties dialog box, or use the Set Output Enable method node outside a single-cycle Timed Loop.

This device supports the Number of Synchronizing Registers for Output Data synchronizing register option when used in SCTL output. This option supports the same functionality as the Number of Synchronizing Registers for Output Data option described in the Advanced Code Generation FPGA I/O Properties Page (FPGA Module) topic, with the exception that you can use this option only in a single-cycle Timed Loop. Implement either 0 or 1 synchronizing registers inside the single-cycle Timed Loop. Note that if you configure 0 synchronizing registers outside of the single-cycle Timed Loop, the FPGA VI implements 1 synchronizing register by default.

When the device is within a single-cycle Timed Loop, it must be ready to perform digital I/O before a loop containing digital I/O starts. Poll the Ready output of the Check Status method to determine whether the module is ready. Digital input operations return invalid data if the module is not ready. The module also might ignore or delay digital output operations if it is not ready.