Use an FPGA I/O Node configured for reading and writing with this device.

Use the FPGA I/O Node to access the following terminals for this device.

Table 684. Terminals in Software
Terminal Description
ConnectorA/AIx Analog input channel x, where x is the number of the channel. Connector A has AI channels 0 to 7.
ConnectorA/AOx Analog output channel x, where x is the number of the channel. Connector A has AO channels 0 to 1.
ConnectorA/DIOy Digital input/output channel y on Connector A, where y is the number of the channel. Connector A has channels 0 to 19. DIO 16 and DIO 17 are shared with the UART and Console Out application. When the UART or Console Out application is enabled, DIO 16 functions as the UART Rx line, and DIO 17 funxctions as the UART Tx line. Use the FPGA I/O Node, the Set Data Output method, or the Set Data Enable method to access this channel.
ConnectorA/DIO7:0 Digital port consisting of channels 0 to 7. Channel 7 is returned in the MSB, and channel 0 is returned in the LSB.
ConnectorA/DIO15:8 Digital port consisting of channels 8 to 15. Channel 15 is returned in the MSB, and channel 8 is returned in the LSB.
ConnectorB/AIx Analog input channel , where x is the number of the channel. Connector B has AI channels 0 to 7.
ConnectorB/AOx Analog output channel x, where x is the number of the channel. Connector B has AO channels 0 to 1.
ConnectorB/DIOy Digital input/output channel y on Connector B, where y is the number of the channel. Connector B has channels 0 to 19. DIO 16 and DIO 17 are shared with the UART and Console Out application. When the UART or Console Out application is enabled, DIO 16 functions as the UART Rx line, and DIO 17 functions as the UART Tx line. Use the FPGA I/O Node, the Set Data Output method, or the Set Data Enable method to access this channel.
ConnectorB/DIO7:0 Digital port consisting of channels 0 to 7. Channel 7 is returned in the MSB, and channel 0 is returned in the LSB.
ConnectorB/DIO15:8 Digital port consisting of channels 8 to 15. Channel 15 is returned in the MSB, and channel 8 is returned in the LSB.
Onboard I/O Button0, LED0, LED1, LED2, LED3, Inst Trig Out and Inst Trig In. Button0 returns the value of the onboard button status. LED0:3 controls the four onboard LEDs. Inst Trig Out sends the trigger signal to the instrumentation board. Inst Trig In receives the trigger signal from the instrumentation board. Use the FPGA I/O Node to access these channels.
Note   When the application board is turned off, the digital outputs go into tristate and the analog outputs go to 0 V. When the power is turned on, the digital outputs and the analog outputs go to the value that was last set. For the digital outputs, this happen immediately. For the analog outputs, there is a delay for the values to go from 0 V to the last written value. If an analog output operation is invoked while this is happening, it gets held off and may potentially affect the loop timing.

Arbitration

Configure the arbitration settings for the DIO channels of this device in the Advanced Code Generation page of the FPGA I/O Properties dialog box. The default arbitration setting is Never Arbitrate.

I/O Methods

Use the FPGA I/O Method Node to access the following I/O methods for this device.

Table 685. I/O Methods
Method Description
Set Output Data Refer to the FPGA I/O Method Node topic in the LabVIEW FPGA Module Programming Reference Manual for a description of this method.
Set Output Enable Refer to the FPGA I/O Method Node topic in the LabVIEW FPGA Module Programming Reference Manual for a description of this method.

Module Methods

Table 686. Module Methods
Method Description
IO Sample Acquires a single sample from the module. The channel number, terminal mode, and voltage range are configurable at run time.
Note   Do not configure the VI to run an IO Sample method and an AI IO Node in parallel when both are targeted to the same connector. Doing so results in an incorrect reading from the IO Sample method. The AI IO Node still gives the correct reading, but will not be able to meet the specified data rate. The same thing applies to having two IO Sample methods run in parallel when both are targeted to the same connector.

Properties

Table 687. Module Properties
Property Description
Conversion Time (ticks) Sets the convert to convert period when scanning through a channel List. This property allows users to set a minimum convert to convert period of 1 us and a maximum of 1 ms. This property is in the unit of ticks, with a tick rate of 40MHz or a tick resolution of 25 ns. This property does not affect the conversion time of the IO Sample method.
UART Enable Enables or disables the UART usage through DIO 16 and DIO 17 for both Connector A and Connector B. UART is disabled by default.
Console Out Enable Reads the Console Out settings. This property is applicable for Connector A only.
Terminal Mode Sets the terminal mode for a channel as RSE (referenced single-ended) or DIFF (differential). This property overwrites the value you configure in the FPGA I/O Properties dialog box.
Voltage Range Sets the input range for a channel as ±10 V, ±5 V, ±2 V, or ±1 V. This property overwrites the value you configure in the FPGA I/O Properties dialog box.

Single-Cycle Timed Loop

This device supports the single-cycle Timed Loop for digital I/O only. To configure the number of output synchronizing registers or input synchronizing registers for the channels on this device, use the Advanced Code Generation page of the FPGA I/O Properties dialog box.