FPGA I/O Node

You can use an FPGA I/O Node configured for reading with this device.

Terminals in Software

Use the FPGA I/O Node to access the following terminals for this device.

Table 508. Terminals in Software
Terminal Description
RF In/I Returns the I data that comes from the RF IN connector.

The I and Q data from each module must be accessed from within the same FPGA I/O Node.

Do not access I and Q data on multiple modules in the same FPGA I/O Node if the modules are not synchronized or do not use the same data rate.
RF In/Q Returns the Q data that comes from the RF IN connector.

The I and Q data from each module must be accessed from within the same FPGA I/O Node.

Do not access I and Q data on multiple modules in the same FPGA I/O Node if the modules are not synchronized or do not use the same data rate.
Onboard Clock Provides access to the onboard clock in LabVIEW. The onboard clock frequency is 12.288 MHz. Use the FPGA I/O Node in a single-cycle Timed Loop to access this channel.

Export the Onboard Clock of the module to access this channel.
Start Channel that controls when the module starts acquiring IQ data.

If you write TRUE to the Start channel, the module starts acquiring data. When the module is acquiring data, you must write TRUE to the Stop channel before you can access properties for this module.

If you write FALSE to the Start channel, no operation is performed.
Stop Channel that controls when the module stops acquiring data.

If you write TRUE to the Stop channel, the module stops acquiring data. When the module is acquiring data, you must write TRUE to the Stop channel before you can access properties for the module.

If you write FALSE to the Stop channel, no operation is performed.
Note For an example of using the Start and Stop channels, refer to the NI 9770 Getting Started VI in the labview\examples\CompactRIO\Module Specific\NI 9770\NI 9770 Getting Started\NI 9770 Getting Started.lvproj directory.

Arbitration

This device supports only the Arbitrate if Multiple Requestors Only option for arbitration. You cannot configure arbitration settings for this device.

I/O Methods

This device does not support any I/O methods.

Module Methods

Use the FPGA I/O Method Node to access the following module methods for this device.

Table 509. Module Methods
Method Description
Configure RF In Configures the RF center frequency of the module and input signal reference level.
  • Center Frequency—Specifies in Hz the desired RF center frequency that the module should tune to.
  • Reference Level—Specifies in dBm the expected total power of the RF input signal.
  • LO Source—Optional parameter that specifies the source of the LO signal that the module uses for RF downconversion. Options are Internal or LO In. When Internal, the module uses the internal LO signal that originates from within the module. When LO In, the module uses the signal that is connected to the LO IN connector on the module.
  • LO In Frequency—Optional parameter that specifies the frequency in Hz of the signal connected to the LO IN connector on the module. When you set the LO Source to LO In, you must connect a signal to the LO IN connector on the module and use this parameter to specify the frequency of that signal.
  • Downconverter Gain—Returns the net signal gain in dB of the RF downconverter. Use this parameter to scale the IQ data to the proper power level, as seen at the RF IN connector on the module.
    Note For an example of how to use Downconverter Gain to scale the IQ data, refer to the NI 9770 Getting Started VI in the labview\examples\CompactRIO\Module Specific\NI 9770\NI 9770 Getting Started\NI 9770 Getting Started.lvproj directory.
    		•
    Check Cached Status Returns the following status information that reports whether various conditions occurred on the module since the last execution of the Check Cached Status method:
  • IQ Data Overflow—Returns a Boolean value. A value of TRUE indicates that the RF input subsystem tried to acquire a signal that is larger in amplitude than the ADC can accurately measure using the current hardware gain configuration. This problem may result from using a reference level that is too low for the supplied input signal.
  • LO PLL Unlocked—Returns a Boolean value. A value of TRUE indicates that the LO PLL is in an unlocked state. The LO PLL must be locked in order to ensure that correct data is acquired from the module.
  • Sample Clock PLL Unlocked—Returns a Boolean value. A value of TRUE indicates that the sample clock PLL is in an unlocked state. When synchronizing multiple modules, the sample clock PLL must be locked in order to ensure that the modules are synchronized properly.

    • I/O Properties

    This device does not support any I/O properties.

    Module Properties

    Use the FPGA I/O Property Node to access the following module properties for this device.

    Table 510. Module Properties
    Property Description
    Data Rate Sets the rate at which the module acquires IQ data.
    Peak RF In Power Returns the peak signal power level in dBm that was measured at the RF IN connector across the full RF frequency range of the module. The peak is cleared when this property is read.
    Note   This value only updates while the module is acquiring IQ data. When the acquisition stops, this property returns the last measured peak signal power level.
    LO Out Enabled When set to TRUE, the module drives the LO signal to the LO OUT connector on the module. This property is used to share the LO signal across multiple NI 9770 modules.

    This property cannot be set to FALSE when the LO Source is set to LO In. The module always drives LO OUT when using an external LO signal on the LO IN connector on the module.
    Downconverter Gain Returns the net signal gain in dB of the RF downconverter. Use this parameter to scale the IQ data to the proper power level, as seen at the RF IN connector on the module.
    Note  For an example of how to use Downconverter Gain to scale the IQ data, refer to the NI 9770 Getting Started VI in the labview\examples\CompactRIO\Module Specific\NI 9770\NI 9770 Getting Started\NI 9770 Getting Started.lvproj directory.
    RF Attenuation Configures the amount of RF attenuation in dB that is applied to the input signal.

    The valid parameter range is 0 dB to 30 dB.

    You can read or write to this property. If you write to this property, you must read Downconverter Gain again.
    IF Attenuation Configures the amount of IF attenuation in dB that is applied to the input signal.

    The valid parameter range is 0 dB to 30 dB. You can read or write to this property. If you write to this property, you must read Downconverter Gain again.
    Module ID Returns the Module ID, 0x7827.
    Serial Number Returns the unique serial number of the module.
    Vendor ID Returns the NI vendor ID, 0x1093.

    Single-Cycle Timed Loop

    Use the Onboard Clock channel in the single-cycle Timed Loop. You cannot use the other channels on the NI 9770 with the single-cycle Timed Loop. For information about loop timing for this module, refer to the Understanding Loop Timing (FPGA Interface) topic.