NI 9505 Current Measurement Considerations (FPGA Interface)

The current sense circuit uses a serial bus to transfer the 12-bit current measurement back to the FPGA. This data transfer can take up to 20 µs to complete. Due to this 20 µs delay, sampling the current multiple times during the motor output period is not practical. Since the current waveform through your inductive load is not the same over the entire period of the motor output signal, it is important to sample the current at the halfway point of the ON portion of the actual motor voltage to obtain an approximate average current. To ensure that current is sampled at the correct time, you must compensate for the delays in both the current sense interface and the motor output interface. The following figure demonstrates how to determine the correct time to sample the current.

Add the following logic into the FPGA VI for the Current Sense I/O node terminal to correctly compensate for the signal offsets and sample the current the appropriate amount of clock ticks after the falling edge of the commanded motor signal. The formula is based on specified typical delays.

where	tcmd_to_current_sense	is the time from the falling edge of the commanded motor signal until the Current Sense terminal of the LabVIEW FPGA I/O node is executed
	td1 = 750 ns + 170 ns	is the delay between the active edge of the commanded motor signal to the active edge of the actual motor voltage
	tactual_motor_on = tcmd_motor_on - 750 ns
		is the delay from the Current Sense terminal of the LabVIEW FPGA I/O node call until the current is sampled
	fclk	is the FPGA clock rate
	tcmd_motor_off = T - tcmd_motor_on
	T	is the commanded motor period, typically 20 kHz

The equation further reduces to:

To convert t_{cmd_to_current_sense} to the number of LabVIEW FPGA clock ticks, multiply by f_clk. Refer to NI 9505 Motor Output and Current Sense Example for a sample motor signal calculation.