FPGA I/O Node

Use an FPGA I/O Node configured for reading with this device.

Terminals in Software

Use the FPGA I/O Node to access the following terminals for this device.

Table 392. Terminals in Software
Terminal Description
DIx Digital input channel x, where x is the number of the channel. The NI 9411 has DI channels 0 to 5.
DI5:0 Digital port consisting of channels 0 through 5.
  • Channel 5 is returned in bit 5.
  • Channel 0 is returned in bit 0.
  • Bits 6 and 7 return a zero.

Arbitration

This device supports only the Never Arbitrate option for arbitration. You cannot configure arbitration settings for this device.

I/O Methods

Use the FPGA I/O Method Node to access the following I/O methods for this device.

Table 393. I/O Methods
Method Description
Wait on Any Edge Pauses the execution of the I/O Method Node until the next falling or rising edge of the digital signal. The Timeout input specifies in FPGA clock ticks how long the Wait on Any Edge method waits for the next falling or rising edge. A value of 0 causes the method to time out immediately, a negative value causes the method to wait indefinitely, and a positive value causes the method to wait for that number of clock ticks before timing out.
Wait on Falling Edge Pauses the execution of the I/O Method Node until the next falling edge of the digital signal. The Timeout input specifies in FPGA clock ticks how long the Wait on Falling Edge method waits for the next falling edge. A value of 0 causes the method to time out immediately, a negative value causes the method to wait indefinitely, and a positive value causes the method to wait for that number of clock ticks before timing out.
Wait on High Level Pauses the execution of the I/O Method Node until the digital signal is high. The Timeout input specifies in FPGA clock ticks how long the Wait on High Level method waits for the next high level. A value of 0 causes the method to time out immediately, a negative value causes the method to wait indefinitely, and a positive value causes the method to wait for that number of clock ticks before timing out.
Wait on Low Level Pauses the execution of the I/O Method Node until the digital signal is low. The Timeout input specifies in FPGA clock ticks how long the Wait on Low Level method waits for the next low level. A value of 0 causes the method to time out immediately, a negative value causes the method to wait indefinitely, and a positive value causes the method to wait for that number of clock ticks before timing out.
Wait on Rising Edge Pauses the execution of the I/O Method Node until the next rising edge of the digital signal. The Timeout input specifies in FPGA clock ticks how long the Wait on Rising Edge method waits for the next rising edge. A value of 0 causes the method to time out immediately, a negative value causes the method to wait indefinitely, and a positive value causes the method to wait for that number of clock ticks before timing out.

Module Methods

Table 394. Module Methods
Method Description
Check Status Returns a Boolean value that indicates whether the module is ready.
Note   During the first 2 seconds after you reset the FPGA VI, the error terminals on the Check Status method may not correctly report certain types of errors.

I/O properties

This device does not support any I/O properties.

Module Properties

Use the FPGA I/O Property Node to access the following module properties for this device.

Table 395. Module Properties
Property Description
Module ID Returns the module ID.
Serial Number Returns the unique serial number of the module.
Vendor ID Returns the NI vendor ID, 0x1093.

Single-Cycle Timed Loop

This device supports the single-cycle Timed Loop. Configure the number of input synchronizing registers for the channels of this device in the Advanced Code Generation page of the FPGA I/O Node Properties dialog box.

When the module is within a single-cycle Timed Loop, it must be ready to perform digital input before a loop containing digital input starts. Poll the Ready output of the Check Status method to determine whether the module is ready. Digital input operations return invalid data if the module is not ready.

While the module is performing digital input within a single-cycle Timed Loop, do not perform property reads or remove the module from the chassis. Doing either of these actions causes the module to be unable to perform digital input and the Ready output of the Check Status method to return FALSE.

FPGA Target Clock Support

This device supports only top-level FPGA target clock rates and single-cycle Timed Loop clock rates that are multiples of 40 MHz, such as 40 MHz, 80 MHz, 120 MHz, and so on.