FPGA I/O Node

Use an FPGA I/O Node configured for reading and writing with this device.

Table 327. Terminals in Software
Terminal Description
AIx Analog input channel x, where x is the number of the channel. The NI 9381 has AI channels 0 to 7.
AOx Analog output channel x, where x is the number of the channel. The NI 9381 has AO channels 0 to 3.
DIOx Digital input/output channel x, where x is the number of the channel. The NI 9381 has DIO channels 0 to 3.
DIO3:0 Digital port consisting of channels 0 through 3. Channel 3 is returned in the MSB, and channel 0 is returned in the LSB.
Caution AI and AO operations that are run concurrently may exhibit jitter. Access both subsystems using a single I/O Node to avoid jitter in your application. Refer to Avoiding Timing Uncertainty for more information.

Arbitration

Analog input and analog output channels of this device support only the Arbitrate if Multiple Requestors Only option for arbitration. You cannot configure arbitration settings for analog input and analog output channels of this device.

You can configure the arbitration settings for digital output channels of this device in the Advanced Code Generation page of the FPGA I/O Properties dialog box. The default arbitration setting is Never Arbitrate.

Digital input channels of this device support only the Never Arbitrate option for arbitration. You cannot configure arbitration settings for the digital input channels of this device.

I/O Methods

Use the FPGA I/O Method Node to access the following I/O methods for the DIO channels of this device.

Table 328. I/O Methods
Method Description
Set Output Data Refer to the FPGA I/O Method Node (FPGA Module) topic for a description of this method.

This method is available only when you set the DIO line direction to output. You can set the DIO line direction in the C Series Module Properties dialog box.
Set Output Enable Sets the line direction of the digital channel or the DIO3:0 digital port.

Refer to the FPGA I/O Method Node (FPGA Module) topic for more information on this method.

This method can introduce jitter in an analog input or analog output loop.

This method is available only when you enable programmable DIO line changes on the module. Enable programmable DIO line changes on the module in the C Series Module Properties dialog box.
Wait on Any Edge Pauses the execution of the I/O Method Node until the next falling or rising edge of the digital signal. The Timeout input specifies in FPGA clock ticks how long the Wait on Any Edge method waits for the next falling or rising edge.
  • A value of 0 causes the method to time out immediately.
  • A negative value causes the method to wait indefinitely.
  • A positive value causes the method to wait for that number of clock ticks before timing out.
Note   This method is not available on the DIO3:0 port. For the first two seconds after resetting the FPGA VI, the time out will not start counting until the module is identified.
Wait on Falling Edge Pauses the execution of the I/O Method Node until the next falling edge of the digital signal. The Timeout input specifies in FPGA clock ticks how long the Wait on Falling Edge method waits for the next falling edge.
  • A value of 0 causes the method to time out immediately.
  • A negative value causes the method to wait indefinitely.
  • A positive value causes the method to wait for that number of clock ticks before timing out.
Note   This method is not available on the DIO3:0 port. For the first two seconds after resetting the FPGA VI, the time out will not start counting until the module is identified.
Wait on High Level Pauses the execution of the I/O Method Node until the digital signal is high. The Timeout input specifies in FPGA clock ticks how long the Wait on High Level method waits for the next high level.
  • A value of 0 causes the method to time out immediately.
  • A negative value causes the method to wait indefinitely.
  • A positive value causes the method to wait for that number of clock ticks before timing out.
Note   This method is not available on the DIO3:0 port. For the first two seconds after resetting the FPGA VI, the time out will not start counting until the module is identified.
Wait on Low Level Pauses the execution of the I/O Method Node until the digital signal is low. The Timeout input specifies in FPGA clock ticks how long the Wait on Low Level method waits for the next low level.
  • A value of 0 causes the method to time out immediately.
  • A negative value causes the method to wait indefinitely.
  • A positive value causes the method to wait for that number of clock ticks before timing out.
Note   This method is not available on the DIO3:0 port. For the first two seconds after resetting the FPGA VI, the time out will not start counting until the module is identified.
Wait on Rising Edge Pauses the execution of the I/O Method Node until the next rising edge of the digital signal.
The Timeout input specifies in FPGA clock ticks how long the Wait on Rising Edge method waits for the next rising edge.
  • A value of 0 causes the method to time out immediately.
  • A negative value causes the method to wait indefinitely.
  • A positive value causes the method to wait for that number of clock ticks before timing out.
Note This method is not available on the DIO3:0 port. For the first two seconds after resetting the FPGA VI, the time out will not start counting until the module is identified.

Module Method

Use the FPGA I/O Method Node to access the following module method for this device.

Table 329. Module Method
Method Description
Check Status Returns a Boolean value that indicates whether the module is ready.

I/O Properties

Use the FPGA I/O Property Node to access the following I/O properties for AI and AO channels of this device.

Table 330. I/O Properties
Property Description
LSB Weight Returns the LSB weight in nV/LSB for the channel. Use this value to convert and calibrate NI 9381 data if you set the Calibration Mode to Raw in the C Series Module Properties dialog box.
Offset Returns the calibration offset in nV for the channel. Use this value to convert and calibrate NI 9381 data if you set the Calibration Mode to Raw in the C Series Module Properties dialog box.

Module Properties

Use the FPGA I/O Property Node to access the following module properties for this device.

Table 331. Module Properties
Property Description
Module ID Returns the module ID.
Serial Number Returns the unique serial number of the module.
Vendor ID Returns the NI vendor ID, 0x1093.

Single-Cycle Timed Loop

This device supports the single-cycle Timed Loop.
  • Configure the number of input synchronizing registers for the channels of this device in the Advanced Code Generation page of the FPGA I/O Node Properties dialog box.
  • Configure the number of output synchronizing registers for the channels of this device in the Advanced Code Generation page of the FPGA I/O Properties dialog box.

This device supports the Number of Synchronizing Registers for Output Data synchronizing register option when used in SCTL output. This option supports the same functionality as the Number of Synchronizing Registers for Output Data option described in the Advanced Code Generation FPGA I/O Properties Page (FPGA Module) topic, with the exception that you can use this option only in a single-cycle Timed Loop. You can implement either 0 or 1 synchronizing registers inside the single-cycle Timed Loop. I you configure 0 synchronizing registers outside of the single-cycle Timed Loop, the FPGA VI implements 1 synchronizing register by default.

When the device is within a single-cycle Timed Loop, it must be ready to perform digital I/O before a loop containing digital I/O starts. Poll the Ready output of the Check Status method to determine whether the module is ready. Digital input operations return invalid data if the module is not ready. The module also might ignore or delay digital output operations if it is not ready.

While the digital is performing digital I/O within a single-cycle Timed Loop, do not perform property reads or remove the module from the chassis. Performing any of these actions causes the module to be unable to perform digital I/O and the Ready output of the Check Status method to return FALSE.

FPGA Target Clock Support

This device supports only top-level FPGA target clock rates and single-cycle Timed Loop clock rates that are multiples of 40 MHz, such as:
  • 40 MHz
  • 80 MHz
  • 120 MHz