The following table lists cRIO-906x Controllers.

Table 30. cRIO-906x Controllers
cRIO-906x Controller Model Description
cRIO-9063 667 MHz Dual-Core CPU, 256 MB DRAM, 512 MB Storage, Zynq-7020 FPGA, 4-Slot CompactRIO Controller
cRIO-9064 667 MHz Dual-Core CPU, 512 MB DRAM, 1 GB Storage, and Zynq-7020 FPGA, 4-Slot CompactRIO Controller
cRIO-9065 667 MHz Dual-Core CPU, 512 MB DRAM, 1 GB Storage, Zynq-7020 FPGA, Extended Temperature, 4-Slot CompactRIO Controller
cRIO-9066 667 MHz Dual-Core CPU, 256 MB DRAM, 512 MB Storage, Zynq-7020 FPGA, 8-Slot CompactRIO Controller
cRIO-9067 667 MHz Dual-Core CPU, 512 MB DRAM, 1 GB Storage, Zynq-7020 FPGA, 8-Slot CompactRIO Controller
cRIO-9068 667 MHz Dual-Core CPU, 512 MB DRAM, 1 GB Storage, Zynq-7020 FPGA, Extended Temperature, 8-Slot CompactRIO Controller

cRIO-906x Front Panel

Figure 16. cRIO-9063/9064/9065/9066/9067 Front Panel


  1. USB Device Port
  2. RS-232 Serial Port
  3. RJ-45 Gigabit Ethernet Ports (one or two, depending on model)
  4. USB Host Port
  5. Power Connector
Figure 17. cRIO-9068 Front Panel


  1. Power Connector
  2. RJ-45 Gigabit Ethernet Port 2
  3. RJ-45 Gigabit Ethernet Port 1
  4. USB Host Port
  5. RS-485 Serial Port
  6. RS-232 Serial Port
  7. RS-232 Serial Port

Configuring Controller Settings

Perform the following procedure to configure controller startup settings in Measurement & Automation Explorer (MAX).
  1. Launch MAX.
  2. Locate the controller under Remote Systems.
  3. Select the Controller Settings tab.

To reboot the device into safe mode, press and hold the Reset button for 5 s.

Resetting the Controller also Resets the FPGA

Resetting the device real-time controller resets the FPGA, clears volatile memory and unloads any loaded FPGA bitfile. After reset, the device is put in Sleep Mode and module output channels revert to default output values. Refer to the module documentation for information about Sleep Mode behavior.

Autoloading the FPGA Bitfile on Startup

If you download a bitfile to the device, the bitfile is autoloaded by default at startup. To disable bitfile autoloading, enable the Disable FPGA Startup Application setting in MAX, or click the Erase Firmware button in the RIO Device Setup Utility.