Conversion Timing for the NI ELVIS III (FPGA Interface)

The NI ELVIS III implements a one-element deep pipeline to access the AI channels per connector. This pipeline results in maximum sample rate, but may not result in the best resolution. To achieve better resolution, you will need to add your own loop delay and slow down the sampling rate. When using the FPGA I/O Node to sample channels, the pipeline is automatically managed by the FPGA I/O Node, and the channels within the FPGA I/O Node are sampled in numerical order regardless of the order they appear in the node.

If the first channel request in the FPGA I/O Node does not match the first channel request stored in the module pipeline, there will be a delay before the first sample occurs. This delay is caused by the input settling time, which is required for the input value to reach a steady level before starting conversion.

If the next channel request in the FPGA I/O Node matches the previous channel request, no delay occurs because that channel has already settled. If a change occurs in the Voltage Range setting and Terminal Mode setting,the FPGA I/O Node waits for the settling delay.

When using the IO Sample method, take steps to manage this pipeline in the VIs. To read one channel,make the request one cycle before the sample time.

The following diagram illustrates how the pipeline works within a sequence structure. A typical application would use a loop structure to iterate through a scan list, which is a predefined list of channels and settings, continuously. The sequence structure shows how data moves into the ELVIS III pipeline and then is converted.