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Timeouts

The Input Timeout (ms) and Output Timeout (ms) properties specify timeout values to use with CAN nodes in the FPGA VI block diagram.

Each timeout is a signed 32-bit integer with a resolution of milliseconds, thus allowing a maximum value of approximately 25 days. Special values of 0 (do not wait) and –1 (wait indefinitely) are supported.

The CAN Input function waits for a new CAN frame to be received, then returns that frame. The Input Timeout (ms) specifies how long to wait for a new frame to be received.

If you specify Input Timeout (ms) of 0, the CAN Input node will simply check to see if a new frame has arrived (non-blocking). If a new frame exists, CAN Input returns the frame with an error status of FALSE (success). If no new frame exists, CAN Input returns an error status of TRUE (error). Therefore, in order to poll for new frames using an input timeout of 0, you must enable Error Terminals for the CAN Input node. When an error is returned, you must invoke CAN Input again at a later time to ensure no data is lost.

The communication path from LabVIEW FPGA to the CAN port is implemented as a FIFO. This allows multiple frames to be sent to the CAN module for transmit, thus enabling VIs that generate full bus load.

When the output FIFO is full, the CAN Output node waits for an element to become available, then writes the frame to the FIFO. Output Timeout (ms) specifies how long to wait for a new element to become available, which occurs when a frame from a previous CAN Output transmits successfully onto the network. If you specify Output Timeout (ms) of 0, the CAN Output node returns an error status of TRUE (error) if a new element is not available in the FIFO (non-blocking). When an error is returned, you must attempt CAN Output of the same frame again at a later time.

In addition to the CAN Output node, Output Timeout (ms) also applies to most methods and properties. For example, if Output Timeout (ms) is 0, the Abort Transmit method returns an error if the output FIFO is full. Refer to the Arbitration topic for more information on the output path from LabVIEW FPGA to the CAN port.