3682 Generic Config VI

Reads/writes a configuration register of the attached AIO-3682 module. This VI should be placed within an SCTL at or below 250 MHz. Accessing this setting requires multiple executions of the VI. Use hand shaking for valid execution. Only use one AIO Config VI per FPGA.

	register specifies the address of the register to read/write to.
	channel specifies which channel of the AIO-3682 module the register is accessed from.
	register value in specifies the value to write to the given register.
	input valid allows you to specify TRUE to start a new gain setting read/write transaction. A new read/write will only occur if this parameter is set to TRUE when ready for input was TRUE the previous cycle.
	write (T) specifies whether the register value is modified. If TRUE, register value in is written to the specified register on the AIO-3682 module. If FALSE, the existing register value is read.
	register value out indicates the actual register values of the AIO-3682 module. Index 0 and 1 correspond to channels 0 and 1 respectively. Channels not specified for configuration will report a value of 0.
	output valid indicates whether the last requested register access has completed and the value of register value out is valid.
	ready for input indicates when the VI is in an idle state and ready to perform a new register read/write.