Right-click an FPGA target in the Project Explorer window and select Properties from the shortcut menu to display the FPGA Target Properties dialog box. Select DRAM Properties from the Category list to display this page.

Use this page to configure how LabVIEW implements the DRAM in the project and how LabVIEW arbitrates between DRAM memory items using the same bank.

Note Not all hardware supports using DRAM for memory. Refer to your target hardware documentation for more information about DRAM support.

This page includes the following components:

Option Description
DRAM Bank Specifies which DRAM bank to configure.

Mode—Specifies how to represent the DRAM memory in the project.You can select from the following options:

  • LabVIEW FPGA Memories—(Default) LabVIEW creates a DRAM memory item in the project.
  • Socketed CLIP—LabVIEW uses a socketed-CLIP interface to read and write DRAM memory.
  • Memory Items—Lists the DRAM memory items you created with the Memory Properties dialog box.
  • Grant Time (cycles)—Specifies the amount of time in cycles that LabVIEW grants access to each partition of DRAM memory. LabVIEW grants access to each partition using round robin scheduling.