LabVIEW Electric Motor Simulation Toolkit API Reference

Part 4: Composing a Real HIL System (Electric Motor Simulation Toolkit)

  • Updated2023-02-21
  • 2 minute(s) read

After verifying that the controller monitors the simulated motor, you can place the controller and simulator on separate hardware and compose a real hardware-in-the-loop (HIL) system. In the HIL system, you connect the controller and simulator with I/O modules.

With the Electric Motor Simulation Toolkit, you can run the LabVIEW sample project wizard to create an Electric Motor Simulation sample project, in which I/O modules are configured properly.

Creating a Sample Project

Complete the following steps to create a sample project for simulating a permanent magnet synchronous motor (PMSM) with the finite element analysis (FEA) model.

  1. Select File»Create Project to launch the Create Project dialog box.
  2. On the Choose a starting point for the project page, select Motor Simulation from the Sample Projects category list.
  3. Select Electric Motor Simulation from the project list. Click Next.
  4. On the Configure your new project page, specify the project name and path. For this tutorial, enter PMSM_FEA as the Project Name. Save the project to the C:\Users\Administrator\Documents\LabVIEW Data\PMSM_FEA directory.
  5. In the Motor Settings section, select Permanent Magnet Synchronous Motor as the Type and FEA Model as the Model.
  6. In the Hardware Settings section, select Simulate motor on FPGA.
  7. Click Finish to create the sample project, as shown in the following figure.

Find the sample project documentation in the Project Documentation folder of the project. Refer to the document for details about connecting the hardware by I/O modules, adapting the sample project to hardware, and running the simulation. You also can replace the control algorithm with your own code, run the solution, and verify the control algorithm.

Related Information

Create Project Dialog Box

Supported Motor Types

FEA Model

Part 3: Simulating a PMSM on an FPGA Target

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