The NI-5640R instrument driver and the example programs supplied with the PCI-5640R abstract out the data ports. No detailed knowledge of the data ports is required when developing applications using the NI-5640R VIs or examples. The information in the following section is intended for advanced users who are developing custom I/O driver VIs.

The ADC has three parallel output data ports. Any processing channel can be routed to any data port, so you can funnel all six channels through the same data port. The FPGA receives the data and breaks it into individual channels again before presenting it to the FPGA VI. The FPGA also generates one clock per data port to facilitate data handling.

Multiple DDC channels are combined in a single data port when the bandwidth requirements exceed the capacity of a single DDC channel. NI-5640R VIs automatically use as many channels as needed.

NI-5640R VIs automatically use as many channels as needed, but the following limitations apply:

  • NI-5640R VIs and examples only support a single data stream from each analog input channel.
  • Only port A is supported.
  • The three ports share a common clock, PCLK. By default PCLK is configured as slave (input); however, the PCI-5640R requires it to be configured as a master (ADC drives PCLK).
  • The parallel output data ports can be configured to work in Interleaved IQ Mode (default) or in Parallel IQ Mode. The PCI-5640R only supports the Interleaved IQ Mode configuration.