Configuring I/Q Clock Rates

Observe the following guidelines when configuring I/Q clock rates. Click a signal name for its explanation.

1. DAC_<i>_IQ_Clk = 2 ×  REFCLK_{DAC_<i>} ×  Clock multiplier_{DAC_<i>}  / Interpolation_{DAC_<i>}

   where

   REFCLK_{DAC_<i>} is the specified device reference clock / N_{2 or 3 CDC}. Specify the divisor using the ni5640R CDC Program VI.

   Clock multiplier_{DAC_<i>}(M) is equal to 1 or 4 ≤ M ≤ 20. Configure the clock multiplier using the ni5640R DAC Program VI.

   Interpolation_{DAC_<i>} is the hardware interpolation rate determined by the DAC fixed 4× interpolator times a programmable 2× to 63× CIC interpolating filter. The programmable CIC interpolator can be configured using the ni5640R DAC Profile VI.
   
   
   

2. ADC_<i>_Port_A_Clk =  ENC_{ADC_<i>} × Clock multiplier_{ADC_<i>} / (Predivide Factor_{ADC_<i>} × Decimation_{ADC_<i>})

   where

   ENC_{ADC_<i>} is the device reference clock / N_{0 or 1 CDC}. Specify the divisor using the ni5640R Configure Timebase VI.

   Clock multiplier_{ADC_<i>}(M) is equal to 1 or 4 ≤ M ≤ 20. Configure the clock multiplier using the ni5640R Input Port VI.

   Predivide Factor_{ADC_<i>} (N) is equal to 1, 2, 4, or 8. Configure the predivide factor using the ni5640R Input Port VI.

   Decimation_{ADC_<i>} is the decimation factor for a particular channel in the ADC. Decimation is performed in various filters throughout the processing channel. Each channel includes one CIC filter (decimates by 1 to 32), two FIR-HB filters (each decimates by 2), one DRC filter (decimates by 1 to 16) and one CRCF filter (decimates by 1 to 16). Configure all these filters using the ni5640R ADC Configure DDC VI.

Refer to Related Documentation for where to find component datasheets with more information on internal signal names.