IF Transceivers

Configuring I/Q Clock Rates

  • Updated2023-02-21
  • 2 minute(s) read

Observe the following guidelines when configuring I/Q clock rates. Click a signal name for its explanation.

  1. DAC_<i>_IQ_Clk = 2 ×  REFCLKDAC_<i> ×  Clock multiplierDAC_<i>  / InterpolationDAC_<i>

    where

    REFCLKDAC_<i> is the specified device reference clock / N2 or 3 CDC. Specify the divisor using the ni5640R CDC Program VI.

    Clock multiplierDAC_<i>(M) is equal to 1 or 4 ≤ M ≤ 20. Configure the clock multiplier using the ni5640R DAC Program VI.

    InterpolationDAC_<i> is the hardware interpolation rate determined by the DAC fixed 4× interpolator times a programmable 2× to 63× CIC interpolating filter. The programmable CIC interpolator can be configured using the ni5640R DAC Profile VI.


  2. ADC_<i>_Port_A_Clk =  ENCADC_<i> × Clock multiplierADC_<i> / (Predivide FactorADC_<i> × DecimationADC_<i>)

    where

    ENCADC_<i> is the device reference clock / N0 or 1 CDC. Specify the divisor using the ni5640R Configure Timebase VI.

    Clock multiplierADC_<i>(M) is equal to 1 or 4 ≤ M ≤ 20. Configure the clock multiplier using the ni5640R Input Port VI.

    Predivide FactorADC_<i> (N) is equal to 1, 2, 4, or 8. Configure the predivide factor using the ni5640R Input Port VI.

    DecimationADC_<i> is the decimation factor for a particular channel in the ADC. Decimation is performed in various filters throughout the processing channel. Each channel includes one CIC filter (decimates by 1 to 32), two FIR-HB filters (each decimates by 2), one DRC filter (decimates by 1 to 16) and one CRCF filter (decimates by 1 to 16). Configure all these filters using the ni5640R ADC Configure DDC VI.

Refer to Related Documentation for where to find component datasheets with more information on internal signal names.

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