NI PXIe-5641R Power-On and Reset Conditions

The NI PXIe-5641R sets some hardware circuitry to certain states at power on and at device reset.

Power-On Conditions

Power-on conditions are present upon powering on or restarting the system and until an FPGA VI has been uploaded to the device.

• DIO lines are configured as input.
• Trigger line is configured as input.
• PXI trigger lines are not configured (appear to the bus as high impedance).
• ADC is reset to the component default state.
• DAC is reset to the component default state.
• CDC is reset to the component default state.

Reset Conditions

The following conditions apply to the device state upon FPGA reset.

• DIO lines are configured as inputs.
• Trigger line is configured as input.
• RTSI line configuration is maintained. If RTSI lines were previously configured as outputs, they are driven high.
• ADC state is maintained.
• DAC state is maintained.
• CDC state is maintained.

Download Conditions

The following conditions apply to the device state upon downloading a new FPGA to the NI PXIe-5641R.

• DIO lines are configured as inputs.
• Trigger line is configured as input.
• RTSI line configuration is maintained. If RTSI lines were previously configured as outputs, they are driven high.
• ADC is reset to the component default state.
• DAC is reset to the component default state.
• CDC is reset to the component default state.