PXI Triggers

You can use the FPGA I/O Node to access the eight PXI trigger lines and PXI_STAR trigger line on the PXIe-5624.

PXI trigger lines are bussed across the backplane to all peripheral devices, so they must be reserved by the application to prevent double-driving the lines and potentially damaging third-party PXI Express devices.

Since the eight PXI trigger lines are bidirectional signals, their configuration must include a direction control, which is accessed through an I/O Method.

When developing an FPGA VI that uses these trigger resources, reserve the trigger lines you are using to ensure compatibility with other NI devices.

Refer to the PXI specifications documentation on ni.com/docs for more information about trigger bus requirements.

Reserving PXI Trigger Resources

NI recommends that you reserve the trigger lines used by NI PXI Express devices. If two PXI Express devices try to drive the same trigger line in different applications or if the PXI Express devices are not programmed to work together, the application does not work. You can use Measurement & Automation Explorer (MAX) or the LabVIEW FPGA host VI to reserve trigger lines.

Notice In some cases, third-party PXI Express devices can be damaged if two PXI Express devices try to drive the same trigger line in different applications or if the PXI Express devices are not programmed to work together.

Reserving Trigger Lines in MAX

If you download and run the FPGA VI interactively, you should configure the PXI Express triggers in MAX. MAX maintains the trigger reservation for the NI device even after you cycle power to the PXI Express chassis.

Reserving Trigger Lines in the LabVIEW FPGA Host VI

If you download and run the FPGA VI programmatically, you should reserve the PXI Express triggers in the host VI.

Complete the following steps to reserve a trigger line for an NI PXI Express device using the host VI.

  1. Place the Open FPGA VI Reference function on the block diagram and configure it for the FPGA device and FPGA VI.
  2. Place the Invoke Method function on the block diagram.
  3. Wire the FPGA Reference Out output of the Open FPGA VI Reference function to the FPGA VI Reference In input of the Invoke Method function.
  4. Wire the error out output of the FPGA VI Reference function to the error in input of the Invoke Method function.
  5. Click the Invoke Method function and select Reserve PXI Trigger from the shortcut menu.
  6. Right-click the Trigger input and select Create » Constant. An enum constant is created to help you select the trigger.

To reserve multiple trigger lines, repeat steps 2 to 6 for each trigger line you want to reserve, wiring the FPGA VI Reference Out output of the existing Invoke Method function to the FPGA VI Reference In input of the Invoke Method function that follows it.

Releasing Trigger Lines

LabVIEW releases the trigger reservation for the NI device automatically when you close the FPGA VI reference. You must run the host VI again to reserve the trigger.

Complete the following steps to release a trigger line for an NI PXI Express device.

  1. Place the Open FPGA VI Reference function on the block diagram and configure it for the FPGA device and FPGA VI.
  2. Place the Invoke Method function on the block diagram.
  3. Wire the FPGA VI Reference Out output of the Open FPGA VI Reference function to the FPGA VI Reference In input of the Invoke Method function.
  4. Wire the error out output of the FPGA VI Reference function to the error in input of the Invoke Method function.
  5. Click the Invoke Method function and select Unreserve PXI Trigger from the shortcut menu.
  6. Right-click the Trigger input and select Create » Constant. An enum constant is created to help you select the trigger.

To release multiple trigger lines, repeat steps 2 to 6 for each trigger line you want to release, wiring the FPGA VI Reference Out output of the existing Invoke Method function to the FPGA VI Reference In input of the Invoke Method function that follows it.

Configuring Trigger Pulses

To ensure compatibility with other NI devices, configure trigger pulses on an NI PXI Express device to last for at least two clock cycles of the clock on the receiving device. For example, if the clock on the receiving device is 8 MHz, which is a clock period of 12.5 nanoseconds, the trigger line must be constant for at least 25 nanoseconds, which is two clock cycles of an 8 MHz clock.

Note Regardless of the clock speed, pulses on the trigger line must be constant for at least 18 nanoseconds.

The clocks between an NI PXI Express device and another device may not be perfectly synchronized. If you assert a trigger line on an NI PXI Express device, you cannot determine at what point in the clock period the trigger registers in the receiving flip-flop. If the trigger arrives during the setup or hold time of the receiving flip-flop, you cannot determine the state of the line for that clock period. Asserting the trigger pulse for two clock cycles ensures that at least one clock cycle on the receiving flip-flop registers as a rising edge and transfers as a trigger.

Refer to the PXI specifications documentation on ni.com/docs for more information about trigger timing parameters.