Socketed CLIP allows you to insert HDL IP into an FPGA target, enabling VHDL code to communicate directly with an FPGA VI. Socketed CLIP also allows the CLIP to communicate directly with circuitry external to the FPGA.

The following sections provide information about how to configure your device for use with socketed CLIP.

PXIe-6591R Socketed CLIP

Refer to the following diagram for an overview of the PXIe-6591R socketed CLIP interface.

Figure 5. PXIe-6591R Socketed CLIP Diagram

Refer to the following table for a list of the PXIe-6591R socketed CLIP signals.

Table 10. PXIe-6591R CLIP Signals
Port Direction Clock Domain Description
MGT_RefClk0_p In (pad) N/A Differential input clock that you must connect to an IBUFDS_GTE2 input buffer primitive when this input clock is used in your design.
MGT_RefClk0_n In (pad) N/A
MGT_RefClk1_p In (pad) N/A
MGT_RefClk1_n In (pad) N/A
MGT_RefClks_
ExtPllLocked In Async Indicates the state of the PLL within the clocking logic that provides the Reference Clock to the FPGA MGTs (MGT_
RefClkx signals).

Use this signal with MGT_
RefClks_Valid to gate and/or reset the clocking signals into any CLIP that depends on the MGT_RefClkx signals.
MGT_RefClks_Valid In Async Indicates if the selected clock input to the clocking logic is valid and the PLL within the clocking logic has locked.

Use this signal to gate and/or reset the clocking signals into any CLIP that depends on the MGT_RefClkx signals.

On the rising edge of MGT_
RefClks_Valid, you may need to reset or relock state machines and/or internal PLLs sensitive to MGT_RefClkx signals.
DebugClks(3:0) Out Clock Debug ports to aid in debugging the clocking connections in the CLIP. These ports connect to frequency counters that can monitor the frequency of any clock that you connect to these ports.

Refer to the Debugging Clocks Using Frequency Counters section of ChapterDeveloping Applications for the High-Speed Serial Device, Developing Applications for the High-Speed Serial Device, for details about how to use these signals.
ExportedUser
ReferenceClk Out Clock Reserved for future use.
LED_ActiveRed Out Async The front panel Active indicator’s red LED turns on when this signal is driven high.

The CLIP’s access to this LED may be temporarily overridden to show error conditions, temperature faults, and power faults.

This signal is conditioned with the pulse stretcher to guarantee a minimum assertion time of 100 ms to comply with PXI guidelines and to facilitate visual perception. You can drive this signal asynchronously if you provide a 50 ns minimum assertion time. You can also drive this signal synchronously for a minimum 1 cycle of SocketClk40.
LED_ActiveGreen Out Async The front panel Active indicator’s green LED turns on when this signal is driven high.

The CLIP’s access to this LED may be temporarily overridden to show error conditions, temperature faults, and power faults.

This signal is conditioned with the pulse stretcher to guarantee a minimum assertion time of 100 ms to comply with PXI guidelines and to facilitate visual perception. You can drive this signal asynchronously if you provide a 50 ns minimum assertion time. You can also drive this signal synchronously for a minimum 1 cycle of SocketClk40.
SocketClk40 In Clock A 40 MHz clock that runs continuously regardless of connectivity. This signal is connected to the 40 MHz Onboard Clock signal, which is the default top-level clock for the LabVIEW FPGA VI.
sFrontEndConfiguration
Done In SocketClk40 Asserts high and stays high when the power-on self-configuration (POSC) state machine is finished with configuration.

After the aResetSl signal transitions from high to low, indicating that the CLIP logic should come out of reset, a POSC reconfiguration occurs unconditionally.

The required clocking signals are not valid until after this signal asserts high.
sFrontEndConfiguration
Prepare In SocketClk40 Reserved for future use. NI recommends assigning this signal to sFrontEnd
ConfigurationReady.
sFrontEndConfiguration
Ready Out SocketClk40 Reserved for future use. NI recommends assigning sFrontEndConfiguration
Prepare to this signal.
aResetSl In Async This signal is not required.

This signal is an asynchronous reset signal from the LabVIEW FPGA environment. If you create an input signal to your CLIP and assign it as Reset in the CLIP wizard, that signal is driven as an asynchronous reset signal. Reset all CLIP state machines and logic whenever this signal is logic high.

This signal is driven high when you call the LabVIEW FPGA Reset invoke method. Call Run on the FPGA VI to deassert this signal.

Do not use CLIP inputs from the LabVIEW FPGA VI in the CLIP until aResetSl is deasserted.
Port<0..1>_RX_p(3:0) In (pad) N/A Dedicated MGT receive signals for Port <0..1>.
Port<0..1>_RX_n(3:0) In (pad) N/A
Port<0..1>_TX_p(3:0) Out (pad) N/A Dedicated MGT transmit signals for Port <0..1>.
Port<0..1>_TX_n(3:0) Out (pad) N/A
Port<0..1>_SCL In/Out Async Bidirectional serial clock signal for the two-wire communication interface on the Port <0..1> connector.

Valid values: 0 and Z (open drain).

This signal is also called MODDEF1.

This signal has a 5 kΩ pull up to +3.3V.
Port<0..1>_SDA In/Out Async Bidirectional serial data signal for the two-wire communication interface on the Port <0..1> connector.

Valid values: 0 and Z (open drain).

This signal is also called MODDEF2.

This signal has a 5 kΩ pull up to +3.3V.
Port<0..1>_GPIO_In In Async Active low presence detect signal from pin B2 on the cable connector. You must tie GPIO_OutEnable_n to “1” in order to allow this functionality. This input is driven low by the high-speed connector while it is inserted into the module.
Port<0..1>_GPIO_Out Out Async This signal is unused.
Port<0..1>_GPIO_
OutEnable_n Out Async You must tie this signal to “1” to disable output and allow the B2 pin to function as a presence detect signal.
sPort<0..1>_
EnablePower Out SocketClk40 Enables or disables the power supply to the cable on Port <0..1>.

This signal is active high.
sPort<0..1>_Power
Good In SocketClk40 Indicates that the power supply to the cable for Port <0..1> is enabled.

This signal may deassert if an over-power condition is detected.
DDC_GPIO_In(19:0) In Async These signals are GPIO inputs within the DDC VHDCI connector.

These signals, along with DDC_GPIO_Out(19:0) and DDC_GPIO_OutEnable_
n(19:0), allow control and monitoring of the DIO(19:0) connections on the DDC_
VHDCI connector.
DDC_GPIO_Out(19:0) Out Async These signals are GPIO outputs within the DDC VHDCI connector.

These signals, along with DDC_GPIO_In(19:0) and DDC_GPIO_OutEnable_
n(19:0), allow control and monitoring of the DIO(19:0) connections on the DDC_
VHDCI connector.
DDC_GPIO_OutEnable_
n(19:0) Out Async These signals enable GPIO_Out within the DDC VHDCI connector.

Drive these signals low to enable output.

These signals, along with DDC_GPIO_In(19:0) and DDC_GPIO_Out(19:0), allow control and monitoring of the DIO(19:0) connections on the DDC_VHDCI connector.