RIO Scan Interface
CompactRIO Scan Mode is powered by two technologies, the RIO Scan Interface and the NI Scan Engine, which work together to provide access to physical I/O on CompactRIO. The RIO Scan Interface is a set of FPGA intellectual property (IP) developed by NI that is downloaded to the CompactRIO FPGA and is responsible for I/O module detection, timing, synchronization, and communication. The RIO Scan Interface runs a hardware-timed scan loop, which updates the physical I/O values. Two DMA channels are used to transport I/O data between the FPGA and real-time operating system (RTOS). This implementation provides hardware-timed I/O updates at the pin with less that 500ns of jitter.
Figure 5. Synchronization of the NI Scan Engine and RIO Scan Interface maintains less than 500ns of jitter at the pin.
The RIO Scan Interface contains several components that enable the flexibility and performance it provides. Each I/O module communicates directly with a cartridge controller responsible for detecting the module type and communicating I/O data to and from the module. The cartridge controller is a “soft-core” eight-bit microcontroller, which is instantiated in the FPGA, allowing you to use any supported I/O module without compiling. There are also two prebuilt specialty digital blocks in the RIO Scan Interface, which provide high-speed counter, pulse width modulation (PWM), and quadrature encoder input functionality to any eight channel (or less) digital C Series Module. The specialty digital blocks can be routed to any two slots in the CompactRIO chassis. Additional specialty digital blocks can be added using the LabVIEW FPGA Module. Each cartridge controller communicates with a single cartridge manager, which controls the hardware scan timing, synchronization of I/O modules, and synchronization with the NI Scan Engine. A DMA engine also communicates with the cartridge controllers and cartridge manager to transfer data to and from the real-time controller.
Figure 6. The RIO Scan Interface contains several components, all of which are instantiated in the FPGA.
NI Scan Engine
The NI Scan Engine is a component of LabVIEW Real-Time that runs at a priority above time critical or between time critical and timed structures, which you can configure. Each time the RIO Scan Interface has finished the latest I/O scan, LabVIEW adds the I/O variables to a global scan engine memory map and updates the values of all I/O variables concurrently. However, you can configure each I/O variable node to use either scanned access or direct access. By default, LabVIEW configures I/O variable nodes to use scanned I/O, which uses the scan engine memory map to perform non-blocking I/O reads and writes (see Figure 5). Direct I/O access bypasses the scan engine memory map and communicates directly with the I/O device driver to perform blocking I/O reads and writes (see Figure 5). The NI Scan Engine also publishes the I/O variables to the network, making them available for reading and writing in host applications, test panels, and I/O forcing. The scan engine, not the LabVIEW shared variable engine, handles the network publishing of the I/O variables, which you can disable from the I/O variable properties page.
A timing signal within the FPGA is asserted when the hardware is busy acquiring data from the I/O modules. The period of this hardware scan is determined by the scan rate you specify in the scan engine properties. At the end of each hardware scan the scan engine transfers I/O data between the controller and the FPGA.
Figure 7. A timing signal within the FPGA determines when I/O data is transferred from the FPGA to the real-time controller.
Hybrid Mode (Scan Mode with LabVIEW FPGA)
One of the most powerful features of CompactRIO Scan Mode is the ability to choose individual modules to program directly with the LabVIEW FPGA Module. Using this approach, the modules you select to program directly with LabVIEW FPGA are removed from the I/O scan and the remaining modules communicate with the RIO Scan Interface.
Figure 8. CompactRIO Hybrid Mode under the Hood.
When you compile your LabVIEW FPGA VI, if any I/O modules are configured to use scan mode, then the necessary components of the RIO Scan Interface will be included in the compile. The result is a single bit file that supports the scan mode features for modules configured to use scan mode, as well as your custom FPGA logic that communicates directly with the remaining I/O modules. LabVIEW is intelligent about the compile and only includes the required components of the RIO Scan Interface for a given configuration. For example, if you compile an FPGA VI that only uses one module in scan mode, then only one cartridge controller will be included in the RIO Scan Interface. Specialty digital blocks are also removed if not configured. Therefore, the amount of FPGA space consumed by the RIO Scan Interface, when compiling an FPGA VI, scales with number of modules using scan mode.
Figure 9. When accessing I/O modules in both Scan Mode and LabVIEW FPGA, only required RIO Scan Interface components are compiled.
The convert clocks on all I/O modules are free running when the hardware scan signal is asserted. Each I/O module type has individual conversion timing, and modules of the same type have synchronized conversions. When the hardware timing signal on the FPGA is unasserted the latest I/O conversion value is transferred to the NI Scan Engine. Each module performs as many conversions as possible to provide the most recent I/O values to I/O variables configured for direct I/O access, which bypasses the scan and reads directly from hardware.
Figure 10. Input module timing.
A slow input module may take several hardware scan periods to convert a single channel. In this case the hardware scan triggers a sequence of converts on all channels. No channel values are copied to the scan engine until all channels have finished being converted, then all channel values are transferred together.
Figure 11. Input timing for a slow module.
Output module timing is like input module timing, but the conversions are left justified so that output values are written immediately at the beginning of a scan. Each module performs as many updates as possible during the hardware scan, so that values written to I/O variables configured for direct I/O access will update as quickly as possible.
Figure 12. Output module timing.