Archived: LabVIEW 2009 and 2009 SP1 FPGA Module Known Issues

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This document contains the LabVIEW 2009 FPGA Module known issues that were discovered before and since the release of LabVIEW 2009. Not every issue known to NI will appear on this list; it is intended to only show the severe and more common issues that can be encountered.

The LabVIEW 2009 Platform Known Issues contains a full listing of known issues, including LabVIEW toolkits and modules.

Windows 7

National Instruments is committed to maintaining compatibility with Microsoft Windows technology changes. However, NI has become aware of a number of issues of potential significance regarding Microsoft Windows 7. To learn how Windows 7 affects your use of NI products, visit ni.com/info and enter the Info Code windows7.

Document Organization

The Known Issues Document is divided into two separate tables. The following section displays the issues by issue category.

Known Issues by Category

Please refer to Developer Zone Article LabVIEW Known Issues Categories Defined for an explanation of the categories and what types of issues are in each category.

For those who wish to locate the newly reported issues, we have also have published a section of the known issues table sorted by the date the issue was added to the document.

Known Issues by Date

Contacting NI

Feel free to contact NI regarding this document or issues in the document. If you are contacting NI in regards to a specific issue, be sure to reference the ID number given in the document to the NI representative. The ID number contains the current issue ID number as well as the legacy ID number (use the current ID number when contacting National Instruments). You can contact us through any of the normal support channels including phone, email, or the discussion forums. Visit the NI Website to contact us. Also consider contacting us if you find a workaround for an issue that is not listed in the document so that we can add the workaround to the document.

Known Issues by Category

The following items are known issues in LabVIEW 2009 and 2009 SP1 FPGA Module sorted by Category.

Building and Distributing LabVIEW Applications
171971 TCP must be installed
93395 4GIHITXE Modifying conditional disable symbols requires recompile
95971 Error compiling empty external clock loop
98807 Host VI does not get notified of changes when building an application
354689 Customer designs may fail with an over-mapping error if Output data and enable are synchronous to different clocks
Compatibility
156070 Save for Previous of FPGA IO Nodes from 2009 and later to 8.6 and earlier can cause broken run arrow.
Controls and Indicators
101193 Read/Write Control function allows you to select disabled control
Functions, VIs, and Express VIs
175762 Some applications using Butterworth filters get bigger and more accurate between 8.6 and 2009
150867 "Not supported for current target" message may occur when Preallocate Arrays is not set.
151047 High-Throughput Math Library node fails to compile if pipeline stage exceeds 64
357204 Compound Arithmetic Function may Return Different Results Than the Desktop for Single Point Operations
Miscellaneous
172016 Windows XP Service Pack 2 displays security alert when you launch the LabVIEW FPGA Compile Server
226029 The behavior of the Run button can be confusing when using the THIRD_PARTY_SIMULATION conditional disable symbol.
Upgrade - Behavior Change
133170 LabVIEW 8.6 VIs using High Throughput Add, Subtract,To Fixed-Point, or Multiply may cause a compilation error in LabVIEW 2009
Upgrade - Migration
107560 Interrupt VIs saved to previous versions of LabVIEW are broken
162027 4HG9BGP2 Control VIs from 8.5.x and earlier do not automatically migrate to the FPGA Module 2009 implementation of the Control VIs
172008 Incorrect mutation



ID Known Issue
Building and Distributing LabVIEW Applications
171971

Return
TCP must be installed
Most Windows installations have TCP installed. The LabVIEW FPGA Module communicates with the LabVIEW FPGA Compile Server through TCP. If TCP is not installed, LabVIEW returns the Error Contacting Server message when it attempts to contact the LabVIEW FPGA Compile Server.

Workaround: TCP must be installed.

Reported Version: 2009    Resolved Version: N/A    Added: 08/04/2009
93395
4GIHITXE


Return
Modifying conditional disable symbols requires recompile
If you modify the conditional disable symbols in a project, the FPGA Module requires you to recompile the FPGA VI even if the FPGA VI does not use Conditional Disable structures.

Workaround: Recompile the FPGA VI.

Reported Version: 8.5    Resolved Version: N/A    Added: 08/04/2009
95971

Return
Error compiling empty external clock loop
If you compile an FPGA VI that contains only an empty loop configured to use an external clock, the FPGA Module returns an error.

Workaround: Do not compile an FPGA VI that contains only an empty loop configured to use an external clock.

Reported Version: Saturn    Resolved Version: N/A    Added: 08/04/2009
98807

Return
Host VI does not get notified of changes when building an application
If you make changes to an FPGA VI without saving the host VI, the host VI refers to the old FPGA VI when you build an application.

Workaround: You must open and save the host VI before building an application.

Reported Version: 8.5    Resolved Version: N/A    Added: 08/04/2009
354689

Return
Customer designs may fail with an over-mapping error if Output data and enable are synchronous to different clocks
Users can place Output Data and Enable nodes in different clock domains. This results in a Tri-state buffer on the FPGA that is enabled by a signal in the different clock domain than the data signal. Some FPGA families may not support this configuration, and user's design may fail to compile with an over-mapping error in some situations. For a Virtex 2 compile, the error may look similar to the attached Compilation Error.png file. The situation where it might fail for Virtex 2 is when two IO Nodes are mapped over two adjacent IOBs and the Data and Enable flops for the IOs are synchronous to 3 or more different clocks.

Workaround: The workaround is to modify the VI. Move the Output Enable node into the same clock domain as the Output Data node.

Reported Version: 8.2    Resolved Version: N/A    Added: 07/11/2012
Compatibility
156070

Return
Save for Previous of FPGA IO Nodes from 2009 and later to 8.6 and earlier can cause broken run arrow.
When performing a Save for Previous on FPGA projects containing IO items that are in version 2009 or later, IO Nodes can break when converting to version 8.6 and earlier.

Workaround: Redrop IO Nodes.

Reported Version: 9.0 - 2.1 branch    Resolved Version: N/A    Added: 08/02/2011
Controls and Indicators
101193

Return
Read/Write Control function allows you to select disabled control
If you disable a control, you can still select the control from the Read/Write Control function, which returns error -61059.

Workaround: Do not select the control from the Read/Write Control function.

Reported Version: Saturn    Resolved Version: 2010    Added: 08/04/2009
Functions, VIs, and Express VIs
175762

Return
Some applications using Butterworth filters get bigger and more accurate between 8.6 and 2009
In 8.6, LabVIEW used a 3-multiplier implementation of the Butterworth Filter when you configured the filter with an input word length of 16 bits or less and with the Show coefficient terminal checkbox unchecked. In 2009, LabVIEW uses a 4-multiplier implementation for this configuration. This adds an extra multiply as well as a small amount of extra adder logic to the final implementation on the FPGA. However, the filter results in 2009 will be slightly more accurate, with typical deviations confined to the least significant bit.

Workaround: To modify the Butterworth Filter so that the resulting filter has the same behavior as it did in 8.6, perform the following steps. 1. Right-click the Butterworth Filter on the block diagram and select "Convert to SubVI" from the shortcut menu. 2. Open the SubVI and right-click the Butterworth Filter on the block diagram. 3. Select "Open Front Panel" from the shortcut menu. 4. Click the Convert button to convert the Express VI to a standard SubVI. 5. Open the block diagram of the Butterworth Filter and find the following SubVI: niFPGA I32xI32 MAC+ MSB.vi 6. Replace that SubVI with the following VI: vi.lib\rvi\Analysis\utilities\niFPGA I32xI32 MAC - MSB.vi 7. Save the VIs.

Reported Version: 2009    Resolved Version: 2010    Added: 04/13/2010
150867

Return
"Not supported for current target" message may occur when Preallocate Arrays is not set.
The "Not supported for current target" error may be displayed for FPGA Analysis functions when the FPGA Preallocate Arrays option is not set. The actual error is that this option must be selected.

Workaround: In VI Properties check the Preallocate Arrays option.

Reported Version: 8.6.1    Resolved Version: N/A    Added: 08/02/2011
151047

Return
High-Throughput Math Library node fails to compile if pipeline stage exceeds 64
If the number of pipeline stages exceeds 64, the compile will report "Loop has iterated 64 times. Use "set -loop_iteration_limit XX" to iterate more." This usually happens in configurations of high-throughput math library nodes where the output data width is 64 and throughput is 1 cycle/sample inside SCTL.

Workaround: Reduce the pipeline stages by reducing the output word length or the throughput. If more than 64 pipeline stages are needed, please contact National Instruments support.

Reported Version: 2009    Resolved Version: N/A    Added: 08/02/2011
357204

Return
Compound Arithmetic Function may Return Different Results Than the Desktop for Single Point Operations
The Compound Arithmetic function may execute operations in a different order on the FPGA than on the desktop, producing slightly different results for floating-point operations. The differences include small rounding discrepancies as well as NaN and Inf behavior.

Workaround: Decompose the Compound Arithmetic Function into individual arithmetic functions to force the order of operations to conform to what you expect.

Reported Version: 2012 32-bit    Resolved Version: N/A    Added: 07/10/2012
Miscellaneous
172016

Return
Windows XP Service Pack 2 displays security alert when you launch the LabVIEW FPGA Compile Server
If you have Windows XP Service Pack 2 installed, a security alert dialog box appears when you launch the LabVIEW FPGA Compile Server for the first time. If you select the Keep blocking this program option, the LabVIEW FPGA Compile Server cannot accept incoming connections from a remote computer. Select Unblock this program, despite the security risk to configure your computer to launch the LabVIEW FPGA Compile Server without any changes in server functionality.

Workaround: Refer to the KnowledgeBase (http://digital.ni.com/public.nsf/websearch/91A1EA23DB25BE4386256E54007AE9E8?OpenDocument) for more information about correcting this problem.

Reported Version: 2009    Resolved Version: N/A    Added: 08/04/2009
226029

Return
The behavior of the Run button can be confusing when using the THIRD_PARTY_SIMULATION conditional disable symbol.
Errors that normally break the Run button will not break the Run button if the error occurs within a Conditional Disable structure case defined for THIRD_PARTY_SIMULATION. In this case, you cannot build simulation exports, but you can build other build specifications. In addition, if the VI has errors outside the simulation-specific case and the Run button is broken, you will not be able to build a Simulation Export build specification.

Workaround: * If the Run button is not broken but the simulation-specific code contains errors, LabVIEW produces code generation errors when you try to build the Simulation Export build specification. Fix the broken code before building the simulation export. * If the Run button is broken because of code outside of a case defined for THIRD_PARTY_SIMULATION , you have the following options to work around the issue before building a Simulation Export build specification: 1) Fix the error condition in the code. 2) Use the Diagram Disable structure to disable the broken or target-specific code. 3) Define your own custom conditional disable symbol in the project for the FPGA target you are using, and place the broken code in that case of the Conditional Disable structure.

Reported Version: 2010 32-bit    Resolved Version: N/A    Added: 08/02/2011
Upgrade - Behavior Change
133170

Return
LabVIEW 8.6 VIs using High Throughput Add, Subtract,To Fixed-Point, or Multiply may cause a compilation error in LabVIEW 2009
If you have a VI saved in LabVIEW 8.6 that has High Throughput Add, Subtract, To Fixed-Point, or Multiply, you may run into compilation error -61161 if you compile it in LabVIEW FPGA 2009.

Workaround: This error is due to the new "Execution mode" configuration in those nodes. If you run into this error, please double click the node and change the "Execution mode" to "Outside single-cycle Timed Loop".

Reported Version: 2009    Resolved Version: 2010    Added: 03/30/2010
Upgrade - Migration
107560

Return
Interrupt VIs saved to previous versions of LabVIEW are broken
If you save an FPGA VI that contains an Interrupt VI to a previous version of LabVIEW and open the FPGA VI in a previous version of LabVIEW, the FPGA VI is broken because the Interrupt VI is not executable.

Workaround: You can delete the Interrupt VI and replace it with an Interrupt VI from the current version to resolve the issue.

Reported Version: Saturn    Resolved Version: N/A    Added: 08/04/2009
162027
4HG9BGP2


Return
Control VIs from 8.5.x and earlier do not automatically migrate to the FPGA Module 2009 implementation of the Control VIs
Control VIs from 8.5.x and earlier will work with LabVIEW 2009. However, if you replace these legacy VIs with the current version of these VIs, you might need to adjust terminal names, single-cycle Timed Loop support, and fixed-point support.

Workaround: NA

Reported Version: 9.0 - 2.0 branch    Resolved Version: 2011    Added: 08/04/2009
172008

Return
Incorrect mutation
You must install LabVIEW 2009 and then the FPGA Module 2009 before you mass compile existing VIs. If you mass compile existing VIs before you install the FPGA Module 2009, the following VIs might have mutation issues: Sine Wave Generator, Discrete Delay, Quantizer, Look-Up Table 1D, Analog Period Measurement, Butterworth Filter, FIFO Read, FIFO Write, HDL Interface Node, Open FPGA VI Reference, Read/Write Control, Call VI, Close FPGA VI Reference, Invoke Method, Up Cast, FPGA I/O Method Node, and FPGA I/O Property Node.

Workaround: You must install LabVIEW 2009 and then the FPGA Module 2009 before you mass compile existing VIs.

Reported Version: 2009    Resolved Version: 2010    Added: 08/04/2009

Known Issues by Date

The following items are known issues in LabVIEW 2009 and 2009 SP1 FPGA Module sorted by Date.

101193 Read/Write Control function allows you to select disabled control
107560 Interrupt VIs saved to previous versions of LabVIEW are broken
162027 4HG9BGP2 Control VIs from 8.5.x and earlier do not automatically migrate to the FPGA Module 2009 implementation of the Control VIs
171971 TCP must be installed
172008 Incorrect mutation
172016 Windows XP Service Pack 2 displays security alert when you launch the LabVIEW FPGA Compile Server
93395 4GIHITXE Modifying conditional disable symbols requires recompile
95971 Error compiling empty external clock loop
98807 Host VI does not get notified of changes when building an application
133170 LabVIEW 8.6 VIs using High Throughput Add, Subtract,To Fixed-Point, or Multiply may cause a compilation error in LabVIEW 2009
175762 Some applications using Butterworth filters get bigger and more accurate between 8.6 and 2009
150867 "Not supported for current target" message may occur when Preallocate Arrays is not set.
151047 High-Throughput Math Library node fails to compile if pipeline stage exceeds 64
156070 Save for Previous of FPGA IO Nodes from 2009 and later to 8.6 and earlier can cause broken run arrow.
226029 The behavior of the Run button can be confusing when using the THIRD_PARTY_SIMULATION conditional disable symbol.
357204 Compound Arithmetic Function may Return Different Results Than the Desktop for Single Point Operations
354689 Customer designs may fail with an over-mapping error if Output data and enable are synchronous to different clocks



ID Known Issue
101193

Return
Read/Write Control function allows you to select disabled control
If you disable a control, you can still select the control from the Read/Write Control function, which returns error -61059.

Workaround: Do not select the control from the Read/Write Control function.

Reported Version: Saturn    Resolved Version: 2010    Added: 08/04/2009
107560

Return
Interrupt VIs saved to previous versions of LabVIEW are broken
If you save an FPGA VI that contains an Interrupt VI to a previous version of LabVIEW and open the FPGA VI in a previous version of LabVIEW, the FPGA VI is broken because the Interrupt VI is not executable.

Workaround: You can delete the Interrupt VI and replace it with an Interrupt VI from the current version to resolve the issue.

Reported Version: Saturn    Resolved Version: N/A    Added: 08/04/2009
162027
4HG9BGP2


Return
Control VIs from 8.5.x and earlier do not automatically migrate to the FPGA Module 2009 implementation of the Control VIs
Control VIs from 8.5.x and earlier will work with LabVIEW 2009. However, if you replace these legacy VIs with the current version of these VIs, you might need to adjust terminal names, single-cycle Timed Loop support, and fixed-point support.

Workaround: NA

Reported Version: 9.0 - 2.0 branch    Resolved Version: 2011    Added: 08/04/2009
171971

Return
TCP must be installed
Most Windows installations have TCP installed. The LabVIEW FPGA Module communicates with the LabVIEW FPGA Compile Server through TCP. If TCP is not installed, LabVIEW returns the Error Contacting Server message when it attempts to contact the LabVIEW FPGA Compile Server.

Workaround: TCP must be installed.

Reported Version: 2009    Resolved Version: N/A    Added: 08/04/2009
172008

Return
Incorrect mutation
You must install LabVIEW 2009 and then the FPGA Module 2009 before you mass compile existing VIs. If you mass compile existing VIs before you install the FPGA Module 2009, the following VIs might have mutation issues: Sine Wave Generator, Discrete Delay, Quantizer, Look-Up Table 1D, Analog Period Measurement, Butterworth Filter, FIFO Read, FIFO Write, HDL Interface Node, Open FPGA VI Reference, Read/Write Control, Call VI, Close FPGA VI Reference, Invoke Method, Up Cast, FPGA I/O Method Node, and FPGA I/O Property Node.

Workaround: You must install LabVIEW 2009 and then the FPGA Module 2009 before you mass compile existing VIs.

Reported Version: 2009    Resolved Version: 2010    Added: 08/04/2009
172016

Return
Windows XP Service Pack 2 displays security alert when you launch the LabVIEW FPGA Compile Server
If you have Windows XP Service Pack 2 installed, a security alert dialog box appears when you launch the LabVIEW FPGA Compile Server for the first time. If you select the Keep blocking this program option, the LabVIEW FPGA Compile Server cannot accept incoming connections from a remote computer. Select Unblock this program, despite the security risk to configure your computer to launch the LabVIEW FPGA Compile Server without any changes in server functionality.

Workaround: Refer to the KnowledgeBase (http://digital.ni.com/public.nsf/websearch/91A1EA23DB25BE4386256E54007AE9E8?OpenDocument) for more information about correcting this problem.

Reported Version: 2009    Resolved Version: N/A    Added: 08/04/2009
93395
4GIHITXE


Return
Modifying conditional disable symbols requires recompile
If you modify the conditional disable symbols in a project, the FPGA Module requires you to recompile the FPGA VI even if the FPGA VI does not use Conditional Disable structures.

Workaround: Recompile the FPGA VI.

Reported Version: 8.5    Resolved Version: N/A    Added: 08/04/2009
95971

Return
Error compiling empty external clock loop
If you compile an FPGA VI that contains only an empty loop configured to use an external clock, the FPGA Module returns an error.

Workaround: Do not compile an FPGA VI that contains only an empty loop configured to use an external clock.

Reported Version: Saturn    Resolved Version: N/A    Added: 08/04/2009
98807

Return
Host VI does not get notified of changes when building an application
If you make changes to an FPGA VI without saving the host VI, the host VI refers to the old FPGA VI when you build an application.

Workaround: You must open and save the host VI before building an application.

Reported Version: 8.5    Resolved Version: N/A    Added: 08/04/2009
133170

Return
LabVIEW 8.6 VIs using High Throughput Add, Subtract,To Fixed-Point, or Multiply may cause a compilation error in LabVIEW 2009
If you have a VI saved in LabVIEW 8.6 that has High Throughput Add, Subtract, To Fixed-Point, or Multiply, you may run into compilation error -61161 if you compile it in LabVIEW FPGA 2009.

Workaround: This error is due to the new "Execution mode" configuration in those nodes. If you run into this error, please double click the node and change the "Execution mode" to "Outside single-cycle Timed Loop".

Reported Version: 2009    Resolved Version: 2010    Added: 03/30/2010
175762

Return
Some applications using Butterworth filters get bigger and more accurate between 8.6 and 2009
In 8.6, LabVIEW used a 3-multiplier implementation of the Butterworth Filter when you configured the filter with an input word length of 16 bits or less and with the Show coefficient terminal checkbox unchecked. In 2009, LabVIEW uses a 4-multiplier implementation for this configuration. This adds an extra multiply as well as a small amount of extra adder logic to the final implementation on the FPGA. However, the filter results in 2009 will be slightly more accurate, with typical deviations confined to the least significant bit.

Workaround: To modify the Butterworth Filter so that the resulting filter has the same behavior as it did in 8.6, perform the following steps. 1. Right-click the Butterworth Filter on the block diagram and select "Convert to SubVI" from the shortcut menu. 2. Open the SubVI and right-click the Butterworth Filter on the block diagram. 3. Select "Open Front Panel" from the shortcut menu. 4. Click the Convert button to convert the Express VI to a standard SubVI. 5. Open the block diagram of the Butterworth Filter and find the following SubVI: niFPGA I32xI32 MAC+ MSB.vi 6. Replace that SubVI with the following VI: vi.lib\rvi\Analysis\utilities\niFPGA I32xI32 MAC - MSB.vi 7. Save the VIs.

Reported Version: 2009    Resolved Version: 2010    Added: 04/13/2010
150867

Return
"Not supported for current target" message may occur when Preallocate Arrays is not set.
The "Not supported for current target" error may be displayed for FPGA Analysis functions when the FPGA Preallocate Arrays option is not set. The actual error is that this option must be selected.

Workaround: In VI Properties check the Preallocate Arrays option.

Reported Version: 8.6.1    Resolved Version: N/A    Added: 08/02/2011
151047

Return
High-Throughput Math Library node fails to compile if pipeline stage exceeds 64
If the number of pipeline stages exceeds 64, the compile will report "Loop has iterated 64 times. Use "set -loop_iteration_limit XX" to iterate more." This usually happens in configurations of high-throughput math library nodes where the output data width is 64 and throughput is 1 cycle/sample inside SCTL.

Workaround: Reduce the pipeline stages by reducing the output word length or the throughput. If more than 64 pipeline stages are needed, please contact National Instruments support.

Reported Version: 2009    Resolved Version: N/A    Added: 08/02/2011
156070

Return
Save for Previous of FPGA IO Nodes from 2009 and later to 8.6 and earlier can cause broken run arrow.
When performing a Save for Previous on FPGA projects containing IO items that are in version 2009 or later, IO Nodes can break when converting to version 8.6 and earlier.

Workaround: Redrop IO Nodes.

Reported Version: 9.0 - 2.1 branch    Resolved Version: N/A    Added: 08/02/2011
226029

Return
The behavior of the Run button can be confusing when using the THIRD_PARTY_SIMULATION conditional disable symbol.
Errors that normally break the Run button will not break the Run button if the error occurs within a Conditional Disable structure case defined for THIRD_PARTY_SIMULATION. In this case, you cannot build simulation exports, but you can build other build specifications. In addition, if the VI has errors outside the simulation-specific case and the Run button is broken, you will not be able to build a Simulation Export build specification.

Workaround: * If the Run button is not broken but the simulation-specific code contains errors, LabVIEW produces code generation errors when you try to build the Simulation Export build specification. Fix the broken code before building the simulation export. * If the Run button is broken because of code outside of a case defined for THIRD_PARTY_SIMULATION , you have the following options to work around the issue before building a Simulation Export build specification: 1) Fix the error condition in the code. 2) Use the Diagram Disable structure to disable the broken or target-specific code. 3) Define your own custom conditional disable symbol in the project for the FPGA target you are using, and place the broken code in that case of the Conditional Disable structure.

Reported Version: 2010 32-bit    Resolved Version: N/A    Added: 08/02/2011
357204

Return
Compound Arithmetic Function may Return Different Results Than the Desktop for Single Point Operations
The Compound Arithmetic function may execute operations in a different order on the FPGA than on the desktop, producing slightly different results for floating-point operations. The differences include small rounding discrepancies as well as NaN and Inf behavior.

Workaround: Decompose the Compound Arithmetic Function into individual arithmetic functions to force the order of operations to conform to what you expect.

Reported Version: 2012 32-bit    Resolved Version: N/A    Added: 07/10/2012
354689

Return
Customer designs may fail with an over-mapping error if Output data and enable are synchronous to different clocks
Users can place Output Data and Enable nodes in different clock domains. This results in a Tri-state buffer on the FPGA that is enabled by a signal in the different clock domain than the data signal. Some FPGA families may not support this configuration, and user's design may fail to compile with an over-mapping error in some situations. For a Virtex 2 compile, the error may look similar to the attached Compilation Error.png file. The situation where it might fail for Virtex 2 is when two IO Nodes are mapped over two adjacent IOBs and the Data and Enable flops for the IOs are synchronous to 3 or more different clocks.

Workaround: The workaround is to modify the VI. Move the Output Enable node into the same clock domain as the Output Data node.

Reported Version: 8.2    Resolved Version: N/A    Added: 07/11/2012

Document last updated on 7/13/2012

Glossary of Terms

 

  • Bug ID - When an issue is reported to NI, you may be given this ID or find it on ni.com.  You may also find IDs posted by NI on the discussion forums or in KnowledgeBase articles.
  • Legacy ID – An older issue ID that refers to the same issue.  You may instead find this issue ID in older known issues documents.
  • Description - A few sentences which describe the problem. The brief description given does not necessarily describe the problem in full detail.
  • Workaround - Possible ways to work around the problem.
  • Reported Version - The earliest version in which the issue was reported.
  • Resolved Version - Version in which the issue was resolved or was no longer applicable. "N/A" indicates that the issue has not been resolved.
  • Date Added - The date the issue was added to the document (not the reported date).