Grand Master Selection and Quality
Because clocks cannot be shared directly over the network, TSN-based devices synchronize by measuring and adjusting the relationship between their clock and a reference clock on the network. Although this is a reliable and accurate method, it is fundamental to synchronization performance in TSN systems.
In the IEEE 802.1AS specification, the reference clock—referred to as the grand master (GM) clock—is automatically selected through an election algorithm. The election is based on clock quality, traceability, and priority; if there happens to still be a tie after those are announced, then it comes down to the MAC address of the device.
After the GM is selected, all other devices become slaves and begin adjusting their clocks to follow the GM clock. The result of the adjustment is additional low-frequency phase noise is introduced to the clocks being used on the slaves. However, NI ensures that all C Series module and FieldDAQ device specifications are met when used in NI hardware within supported network topologies with the NI device acting as the GM. You should verify performance in any other situation.
When designing a distributed synchronized measurement system, one of the first things to consider is how all these devices are connected to each other, otherwise known as your system topology. As you are designing your system topology, consider the number of hops in the system. A hop is created as the number of devices increase in a line within the topology, which increases the number of bridges participating in the synchronization. In the following image, the system consists of two hops (assuming the first chassis is the GM).
Figure 1: A TSN topology that consists of two hops (assuming the first chassis is the GM)
Each additional hop, or bridge introduced into the system, adds tens of nanoseconds of uncertainty into the synchronization accuracy. When you review the three main topologies, the line topology has the greatest amount of bridges introduced and participating in synchronization, providing the lowest synchronization accuracy of the three main topologies. The star topology provides the highest synchronization accuracy because there is only a single hop between the GM and the devices. The ring topology adds a redundant link that is exploited automatically to improve the data movement and synchronization, allowing the lowest possible number of hops away from the GM to the furthest device.
Learn more about the system topologies and designing distributed TSN measurement systems.
Module Timing Architectures
To support the broadest possible set of measurement types and channel densities, C Series modules and FieldDAQ devices are supported using several different timing architectures. There are two groups of timing architectures: sample clock timed and oversample clock timed. Both timing architectures rely on clocks to control when samples occur. In most cases, the chassis generates the necessary clocks. On synchronized TSN devices, these chassis clocks are tuned to the same reference frequency, that of the GM, and thus maintain a fixed-phase relationship.
Sample clock-timed modules are operated from a sample clock generated by a timing engine on the chassis. Because the sample clock is derived from a time base that is phase-aligned with the TSN network, the clock is synchronized with other clocks on the IEEE 802.1AS network. The sample clock starts running when a start trigger event occurs. When the start trigger is shared by modules, the data is synchronized. When the modules are identical, the data reflects precisely aligned samples. For different module types, the delays may be different, which affects the precision of the data.
Scanned modules, types of sample clock-timed modules, adds per-channel delays as the single analog-to-digital converter (ADC) must operate separately for each channel being acquired. When synchronizing scanned modules with nonscanned modules, care must be taken to associate samples from the scanned module and other module types.
Oversample clock-timed modules operate from high-precision clocks that run constantly. On TSN devices, these clocks are generated by the chassis itself and are tuned to match other chassis clocks but are not phase aligned. They do not drift from each other, but may be misaligned by up to half a sample period between chassis. Because the clocks run constantly, another signal is required to synchronize the data from these clocks, the sync pulse. This signal indicates when the module should start producing or consuming data. Without this signal, the clock would be synchronized but not the data.
Most oversample clock-timed modules are DSA modules, which oversample and filter to produce the final data. This introduces group delay, which can vary between module types and different configurations of the same modules. On C Series NI-DAQmx modules and FieldDAQ devices, this group delay is present in the data affecting the precision of synchronization.
Learn more about synchronizing analog input C Series modules with NI-DAQmx.