A 1ms transient analysis simulation quickly generates the following waveforms for the output voltage and inductor current in Figure 3.
Figure 3. Transient response of the circuit using the initial component values.
Note that the output voltage, at 3.7V (shown in red in Figure 3), is inconsistent with expectations from theoretical calculations. As a result of the various voltage drops across the BJT and the diode, the expectation is to see a voltage slightly lower than 3.3V, not higher. But on inspection of the BJT waveforms with respect to the drive signal we can see the cause in Figure 4.
The actual BJT turn-on and turn-off events (in green) lag the gate drive signal significantly. The turn-off lag is greater than the turn-on lag, explaining the higher-than-expected output voltage.
By using this simulation of the performance we also uncover a far more serious problem that the BJT spends a significant amount of time in the active region where it consumes a large amount of power. Probing the average power dissipation in the BJT results in 2.5W of power dissipation. This implies not only that the efficiency of the converter is likely below 50% but also that the transistor will probably be destroyed without an impractically large heat-sink
Figure 4. Switching transistor current and voltage waveforms
Luckily this problem can be easily mitigated by placing a small capacitor in parallel with the base resistor as shown in Figure 5.
Figure 5. Capacitor Cb added to the base resistance to reducedelay
This capacitor provides extra current during the turn-on and turn-off transients.
We performed a simple parameter sweep analysis to determine a good value for the capacitor. We have chosen the power dissipated by the transistor as the metric for evaluating the effectiveness of various capacitor values. The following graph shows the average power dissipation of the transistor for various values of the capacitor. From a range of 1pF to 1uF, a value of 10nF appears to provide turn-on/turn-off characteristics that result in the lowest power dissipation. A more standard value for the capacitor, 4.7nF, yields the following results for the output voltage and inductor current.
Figure 6. Results of the parameter sweep simulation over the value of Cb
The output voltage, at 3.1V, is now much more in-line with our expectations. In practice this converter would be operated at a duty cycle higher than 33% to compensate for the various voltage drops which pushes the output voltage below the value expected from the ideal relationship, Duty*Vin.
The inductor current ripple is 298mA, which matches our estimate from the ripple formula, and is below the required maximum.
The voltage ripple evaluated in Figure 7 is 60mV, which is higher than that expected according to the ripple formula; it is also just at the limit of the requirement. The excess ripple is a result of the output capacitor’s ESR. It is preferable to reduce it.
Figure 7. Transient time response of the circuit topology after adding Cb
Simulation provides an interesting insight into the sensitivities of the ripple. For instance increasing the capacitance value from 9.4uF to 100uF reduces the ripple only by 5mV. However it also shows that decreasing the ESR from 200mΩ to 100mΩ reduces the ripple by 15mV. Therefore it may be more effective to decrease the ESR rather than increase capacitance to reduce ripple in our circuit.