As clock speeds and data rates continue to increase, designers of digital integrated circuits are creating new ways to maximize the rate of data being sent into and out of digital devices. One such method is known as double data rate (DDR). With single data rate (SDR) devices, data is latched on either the rising or falling edges of the sample clock. A DDR device latches data on both the rising and falling edges of the sample clock, effectively doubling the data transfer rate without increasing the clock speed. This application note describes DDR and its use with National Instruments digital waveform generator/analyzer devices.
When the data rate multiplier is configured for DDR operation, NI digital waveform generator/analyzer devices generate or acquire data twice per sample clock period. The digital waveform generator/analyzer trades channel count for data rate by generating or acquiring on half the number of channels but at twice the rate. The phase relationship of the data to the Sample clock is determined by the data position. While you can configure the data rate multiplier for acquisition and generation separately, you cannot have both SDR channels and DDR channels in the same direction.
As noted above, when using DDR the main consideration to account for is data width. Data width is a function of your data rate multiplier. Since data width refers to how large your sample is in bytes, using DDR mode effectively halves your allowable data width. For example, on a device with 16 channels, you can generate or acquire data on all 16 channels when using SDR. For the same device with its data rate multiplier configured for DDR, you can generate on only eight channels (channels 0-7) and acquire on the other eight (8-15).
The following figure shows a comparison of SDR and DDR:
Figure 1 - The figure above shows how SDR and DDR work while sampling data on output.
Notice how the data output is generated on both the rising and falling edges of the clock when in DDR mode.
While acquiring digital signals DDR works very similar to the above shown generation method. Instead of sampling at every rising edge of a clock, samples are also acquired at falling edges of the clock.
Figure 2: The above figure shows how DDR can be used to sample at both edges of a clock for an acquisition session.
Device user manuals will describe and instrument's DDR capabilities. For information on setting up a non-native DDR acquisition or generation on unsupported devices, see the following Application Note:
To enable DDR generation or acquisition on NI HSDIO devices with native DDR support, use the HSDIO property located under Advanced >> Data Rate Multiplier and set it to Double Data Rate. The C/C++ environment equivalent property is