The following installer contains host VIs, FPGA templates, and example projects for performing waveform data acquisition on NI RIO hardware. The configuration and acquisition VIs incorporate optimizations and best practices for the RIO platform, and you can easily modify the examples to jump-start your application development.
Many reconfigurable I/O (RIO) applications acquire continuous blocks of data from multiple synchronized NI C Series modules. This tutorial presents CompactRIO data acquisition VIs that incorporate RIO optimizations and best practices, and offers several examples to jump-start your application development.
VIs combine common acquisition functions into logical blocks, which support many different acquisition modes. Example programs demonstrate various flavors of continuous and finite acquisitions.
VIs can present data with the NI LabVIEW waveform datatype to easily integrate with other common LabVIEW software components. The waveform datatype bundles the acquired data with its sampling period, timestamp, and channel properties (like channel name).
VIs push calibration and scaling operations onto the field-programmable gate array (FPGA) to free host resources.
VIs perform a full complement of error checking including DMA FIFO overflow (data buffer has filled up causing data to be dropped), module underflow (FPGA code execution takes too long, causing your module to sample slower than intended), and start/read/stop timeouts.
Included Read functions use a polling architecture, which gives the user control over CPU usage during data acquisition.
The examples are very flexible and can adapt to many different hardware combinations. For most applications, only the FPGA VI needs to be modified.
cRIO Wfm Examples.lvproj demonstrates common acquisition modes and how to link host code to FPGA code. The example is installed as a Sample Project in your LabVIEW environment and can be opened from the Create Project... option in the launch window.
The project itself is also located at:
National Instruments\LabVIEW [Version]\ProjectTemplates\Source\cRIOWfm
You will likely need to move this example to another FPGA target and then use a "save as" on all VIs to avoid editing the source install. For more information refer to ni.com/info and enter info code fpgaex.
Figure 3.Example Project Overview
The Host Examples section demonstrate various flavors of continuous and finite acquisition.
The FPGA Templates section has one template for Delta Sigma based modules and one template for SAR based modules. Under the FPGA target you will also find the DMA Channel, and a PDF document describing how to customize the FPGA VIs for your hardware configuration.
Finite Acquisition: The finite acquisition mode tells the FPGA to acquire a certain number of samples and then terminate the acquisition. In this acquisition mode, ConfigTiming.vi calls BufferConfig.vi and sets the host application's data buffer size equal to the number of points in the finite acquisition.
Finite Acquisition with Subset Reads: Again a finite acquisition allocates exactly enough memory to hold all of the requested samples per channel. Read(poly).vi has a control named Samps Read per Chan that you can use to specify the block size returned by each call, so you can read the finite acquisition in multiple subsets - a useful feature in many processing applications.
Finite Acquisition with Rearming Software Start Trigger: When a finite acquisition terminates, the FPGA automatically rearms itself for another acquisition. You simply need to call Start.vi to perform another finite acquisition.
Continuous Acquisition: The continuous acquisition mode tells the FPGA to acquire points indefinitely until a stop command is issued or until an error is encountered (FIFO overflow, module underflow, and so on). In this acquisition mode, use BufferCfg.vi to explicitly set the host application's data buffer to be many times larger than the read size. The examples use a 10X size by default. If the host application's data buffer fills, then the FPGA experiences a FIFO overflow causing the acquisition to stop.
Continuous Acquisition with Start/Stop or Pause Functionality: If a finite acquisition is too large for the amount of memory available on the host controller, then perform a continuous acquisition for a finite period of time via a state machine. When you call Stop.vi, the FPGA stops the acquisition and immediately rearms itself waiting for Start.vi to be called. The stop VI also flushes the host application's data buffer so subsequent acquisitions do not return old data.
For each of the controllers listed, the CompactRIO Continuous Acquisition Example acquired data continuously and streamed it to either a local technical data management streaming (TDMS) file, a local binary file, or a remote host through TCP/IP. The bandwidth values represent the amount of data that can be streamed indefinitely (or until the hard drive is filled).