Memory Test Reference Design

Publish Date: May 17, 2012 | 0 Ratings | 0.00 out of 5 | Print

1. Overview

This document discusses the details of Bit Error Rate Testing (BERT) testing using National Instruments hardware and software. To learn more about the hardware components of this test system, click here. To learn more about the software components of this test system, click here. To return to the Digital Semiconductor Validation Test Reference Architecture main page, click here.

Today, numerous gadgets require some form of memory for their basic operations. Devices ranging from cell phones to computers can have memory embedded in them, or ports into which external memory can be plugged in. A vital part of the production and testing of these devices is memory testing. This paper discusses the details of how to use National Instruments hardware and software to perform such memory tests.

A memory test consists of testing the various components of the memory, including testing for functional performance of the address and data lines, and timing tests. The lines are tested using various patterns such as marching ones or pseudo random values. The values are then read back and compared against expected data for errors.

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2. Hardware Setup

The National Instruments 655x series of high-speed digital (HSDIO) boards, all of which have per pin bidirectional control, are ideally suited for conducting memory tests.For this test, the NI PXI-6552 100 MHz Digital Waveform Analyzer/Generator is used.

The high speed digital instruments offered by National Instruments can be used to connect to the parallel lines of the memory tester, which generates address and control signals and manages the bidirectional data bus. For writing operations, the NI PXI-6552 device will drive the bus; and for read operations the high speed digital device tristates the bus

Figure 1 - Interfacing an NI 655X board with a memory tester


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