Building a Finite State Machine for the NI DE FPGA Board

Publish Date: Jul 23, 2010 | 0 Ratings | 0.00 out of 5 |  PDF

Overview

In this lab, students will learn how to model a finite state machine in Verilog HDL using Xilinx ISE Tools and the NI DE FPGA Board. Students will learn how to model a specified sequence counter using three always blocks. This lab allows students to compare and contrast between using single always blocks and three always blocks. After design, students will test and verify their programs in hardware.

1.  Building a Finite State Machine Lab 

This is a free downloadable lab to be used with the NI DE FPGA Board, and Xilinx ISE tools.  Students can begin to learn how to program an FPGA with Verilog by referring to the Building a Finite State Machine Lab, downloading the support files, and completing the exercise steps. 

To begin, please download the attached PDF document. 

Software Requirements


Application Software: Xilinx ISE tools

Hardware Requirements


Driver: NI Digital Electronics FPGA Board Hardware Driver

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Attachments:

fsm_lab.pdf

fsm_lab.zip


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