NI PXIe-5641R Product In-Depth

Publish Date: Jan 02, 2014 | 0 Ratings | 0.00 out of 5 |  PDF

Overview

The NI PXIe-5641R integrates an intermediate frequency (IF) transceiver with a Xilinx SX95T Virtex-5 field-programmable gate array (FPGA). The FPGA is programmable using the NI LabVIEW FPGA Module. With LabVIEW FPGA, you can create custom measurement and digital signal processing algorithms without low-level hardware description languages or board-level design. LabVIEW FPGA is distinctly suited for FPGA programming because it clearly represents the parallelism and data flow inherent in FPGAs. This tutorial examines the architecture and components that make up the NI PXIe-5641R transceiver along with its theory of operation.

Table of Contents

  1. Technical Features
  2. Programming the NI PXIe-5641R
  3. Additional Resources

1. Technical Features

The NI PXIe-5641R front panel provides connectors for two analog inputs, two analog outputs, an external clock input, and a trigger input along with an auxiliary connector for seven digital I/O pins. Figure 1 shows the NI PXIe-5641R block diagram.

Figure 1. Block Diagram Showing System Components

Analog Input

The NI PXIe-5641R has two independent, single-ended, AC-coupled, 14-bit AI channels. The AI signal goes through a lowpass filter before being converted into a differential signal that is connected to the AD 6654 analog-to-digital converter (ADC).  This ADC contains a six-channel digital downconverter (DDC), which processes the digitized data and performs downconversion (digital frequency translation) and RF channel selection.  Thus, an analog IF signal at the ADC input is converted into a digital I/Q stream by the DDC. This I/Q stream is routed to the FPGA. Each DDC can operate concurrently in a polyphase manner on the digitized data stream to maximize the real-time bandwidth capability of the ADC/DDC integrated circuit (IC).  

Analog Output

The NI PXIe-5641R provides two analog output connectors. The AO signal is generated from an AD 9857 14-bit digital-to-analog converter (DAC). The DAC also has an integrated digital upconverter (DUC) that performs the following tasks needed to process a signal for transmission:

  • Baseband to IF conversion using a digital mixer and digital NCO
  • Interpolation filter to increase the sample rate to meet the IF carrier frequency requirements
  • Inverse CIC compensation for the interpolation filter

Pulse shaping filtering for the output data is not performed by the DAC – you must perform it in your FPGA application. You can define your own pulse shaping filter in LabVIEW FPGA or you can use the LabVIEW FPGA RF Communication Library, which includes pulse shaping filters.

Digital I/O

The NI PXIe-5641R has seven digital I/O (DIO) channels that you can access from the DIO (AUX) connector on the device front panel. DIO lines are direction-configurable by the pin as input or output.

FPGA

You use the Xilinx SX95T Virtex-5 FPGA on the NI PXIe-5641R to execute the LabVIEW FPGA VIs you develop. This FPGA is connected to all the resources on the device (ADC, DAC, clock distribution circuit [CDC], DIO, EXT TRIG) using point-to-point connections. It has 94,208 logic cells, 640 multipliers, and 8,784 kilobits of block RAM.

Trigger

With an external digital pulse, you can trigger the transceiver for acquisition or generation. You can route trigger signals through the TRIG connector on the NI PXIe-5641R front panel. You also can access the trigger line through the FPGA VI as a digital line. This feature does not work if you are using the NI-5640R instrument driver. To use this feature, you must write custom FPGA code (LabVIEW FPGA only). You also can configure the trigger source as any DIO line or one of the PXI trigger lines.

In addition, you can use software to trigger the NI PXIe-5641R and an I/Q power edge trigger to trigger acquisition sessions.

Configuration Description
Onboard Clock The NI PXIe-5641R timebase is a 200 MHz voltage controlled oscillator (VCXO) that you can configure to run independently of other clocks.
External Reference Clocking

You can phase lock the NI PXIe-5641R timebase to two sources:

  • An external frequency reference connected to the CLK IN front panel connector
  • The PXIe_CLK100 signal on the PXI Express backplane

This option is useful when frequency-locking two or more NI PXIe-5641R modules or when locking the NI PXIe-5641R timebase to an external frequency source. Refer to the NI PXIe-5641R specifications for valid reference clock frequency ranges.

Table 1. NI PXIe-5641R Triggering Configurations

The entire NI PXIe-5641R operates in the same clock mode (internal or external). 

PXI Express Bus Interface

The NI PXIe-5641R is a 32-bit PXI Express module with bus-mastering and DMA capabilities. NI LabVIEW software uses DMA transfers to efficiently transfer data between the host PC and the NI PXIe-5641R FPGA at throughput rates >100 MS/s from FPGA to host and >50 MS/s from host to FPGA.  

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2. Programming the NI PXIe-5641R

You can create applications for your IF transceiver using the NI-5640R instrument driver in LabVIEW or you can use the LabVIEW FPGA Module to create your program. More information about each of these methods is provided in the sections below. Your choice for which programming API to use depends on your application needs. The differences between each choice are described in the proceeding sections and summarized in Table 2. 

Table 2. Differences between the NI-5640R Programming APIs

NI-5640R Instrument Driver

The NI-5640R instrument driver offers a fixed personality for your NI PXIe-5641R module. These drivers provide the default personality – two synchronized input and two synchronized output channels. The NI-5640 instrument driver is recommended for taking quick measurements because it requires no FPGA compilation. The driver's palette contains VIs for configuring, initializing, and controlling the NI PXIe-5641R along with other device-specific functions.

Figure 3. Spectral Analyzer Application Using the NI-5640 Instrument Driver (fixed personality drivers)

Figure 3 shows the NI PXIe-5641R Spectrum Analyzer VI, which is one of the example programs that uses the fixed-personality drivers to acquire signals from its analog input. You can find example VIs in the NI Example Finder.

 LabVIEW FPGA

Using the LabVIEW FPGA Module, you can configure the behavior of the FPGA in the NI PXIe-5641R to closely match your system requirements. The behavior of this transceiver then becomes fully user-defined. LabVIEW FPGA offers two methods of programming. The “traditional” method uses the standard first-in-first-out memory buffers (FIFOs), I/O nodes, and register reads and writes. The other method, using NI-5640R asynchronous programming wires, abstracts much of the programming associated with traditional LabVIEW FPGA development and creates asynchronous (non-dataflow) communication between the blocks. This greatly simplifies the development of multirate digital signal processing applications. For a demonstration of programming using asynchronous wires, refer the Introduction to Programming Using Asynchronous Wires tutorial.

Figure 4. A Simple Spectrum Analyzer Application Using the NI-5640R Asynchronous Programming Palette

For a step-by-step tutorial on programming an NI PXIe-5641R, refer to Appendix C: Creating an IF Transceiver Application in the NI PXIe-5641R IF Transceiver Getting Started Guide.

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3. Additional Resources

Reconfigurable I/O Intermediate Frequency Transceivers

Spectral Monitoring Webcast

Software-Defined Radio

Introduction to Programming with Asynchronous Wires

Understanding the Fundamentals of Digital Communications

 

 

 

 

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