NI LabVIEW RIO Evaluation Kit - Additional Exercises

1. Event Counter, Falling Edge

This VI contains an event counter that increments on every falling edge of the input trigger signal. To reset the value of the counter, use the asynchronous reset button on the front panel of the VI.

Download: 

1 - Event Ctr, Falling Edge.zip

Instructions:

1. From the download directory, open Event Ctr, Falling Edge - sbRIO.lvproj.
2. Expand the directory for the Real-Time target, then the FPGA target.
3. Open and run Event Ctr, Falling Edge.vi.

For additional help with this example, see the documentation included in the application.

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2. Event Counter, Programmable Edge  

This VI contains an event counter that increments on the hardware selected edge of the input signal, either rising or falling. To reset the value of the counter, use the reset button on the front panel of the VI.

Download: 

2 - Event Ctr, Programmable Edge.zip

Instructions:

1. From the download directory, open Event Ctr, Programmable Edge - sbRIO.lvproj.
2. Expand the directory for the Real-Time target, then the FPGA target.
3. Open and run Event Ctr, Programmable Edge.vi.

For additional help with this example, see the documentation included in the application.

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3. Quadrature Counter   

This VI uses the quadrature encoder hardware on the evaluation board daughter card to count pulses on the encoder. The VI decodes the A and B pulses and an 8-bit count, displayed on the Front Panel as well as in binary on the evaluation board LEDs, shows the current count position of the encoder. Use the reset button to reinitialize the quadrature encoder count to zero.

Download: 

3 - Quad Ctr.zip

Instructions:

1. From the download directory, open Quad Ctr – sbRIO.lvproj.
2. Expand the directory for the Real-Time target, then the FPGA target.
3. Open and run Quad Ctr.vi.

For additional help with this example, see the documentation included in the application.

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4. Quadrature Counter, Index Save   

This VI interprets a quadrature encoder input using the A and B signals, and also asynchronously saves the current position value on every valid index state. This means that the position value is stored each time a particular configuration of inputs is seen. In this case, a valid index state is defined when Line A, Line B and Input Z are all low.

Download: 

4 - Quad Ctr, Index Save.zip

Instructions:

1. From the download directory, open Quad Ctr, Index Save - sbRIO.lvproj.
2. Expand the directory for the Real-Time target, then the FPGA target.
3. Open and run Quad Ctr, Index Save.vi.

For additional help with this example, see the documentation included in the application.

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5. Two Edge Measurement 

This VI performs a two edge separation measurement between the push buttons PB1 and PB2. The output is the difference in milliseconds between rising edges of PB1 and PB2.

Download: 

5 - Two Edge Measurement.zip

Instructions:

1. From the download directory, open TwoEdge – sbRIO.lvproj.
2. Expand the directory for the Real-Time target, then the FPGA target.
3. Open and run TwoEdge.vi.

For additional help with this example, see the documentation included in the application.

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6. PWM Generation

This VI generates a pulse width modulated output with variable high and low periods. The program uses the potentiometer to vary the duty cycle from 0% to 100%. In addition, use the first toggle switch to select between .5 Hz and 100 Hz PWM frequencies. The result of the PWM is represented on the LEDs.

Download: 

6 - PWM Generation.zip

Instructions:

1. From the download directory, open PWM Out – sbRIO.lvproj.
2. Expand the directory for the Real-Time target, then the FPGA target.
3. Open and run PWM Out.vi.

For additional help with this example, see the documentation included in the application.

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7.  PWM Generation and Measure – Simple 

This VI is divided into two parts - PWM generation and PWM measurement. First, it generates a pulse train on a digital output according to low and high period controls. Next, it measures the same digital signal using a digital input and measures the high and low periods in software.

Download: 

7 - PWM Generation and Measure - Simple.zip

Instructions:

1. From the download directory, open PWM Simple Generation and Measure – sbRIO.lvproj.
2. Expand the directory for the Real-Time target, then the FPGA target.
3. Open and run PWM.vi.

For additional help with this example, see the documentation included in the application.

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8. PWM Generation and Measure – Latched 

This VI is divided into two parts - PWM generation and PWM measurement. It first generates a pulse train on a digital output according to low and high period controls. Changes to these control values take place one full period following the assertion of the Load control. It then measures the same digital signal using a digital input to evaluate the high and low periods in software. The high and low period measurements are updated after the Latch control is asserted.

Download: 

8 - PWM Generation and Measure - Latched.zip

Instructions:

1. From the download directory, open PWM Latched Generation and Measure - sbRIO.lvproj.
2. Expand the directory for the Real-Time target, then the FPGA target.
3. Open and run PWM Latched.vi.

For additional help with this example, see the documentation included in the application.

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9. Look-up Table

This VI demonstrates the functionality of a look-up table (LUT) using the Single-Board RIO hardware. It references a predefined table of values corresponding to a sine waveform. Then, it outputs the waveform on the six LEDs of the evaluation kit daughter board. The program uses the potentiometer on the daughter card to vary the frequency.

Download: 

9 - Look-up Table.zip

Instructions:

1. From the download directory, open LUT - sbRIO.lvproj.
2. Expand the directory for the Real-Time target, then the FPGA target.
3. Open and run Sin LUT.vi

For additional help with this example, see the documentation included in the application.

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10. Butterworth Filter 

This application demonstrates the use of the Butterworth filter on the FPGA as well as Real-Time to FPGA communication. The FPGA generates a noisy sine wave and passes the waveform through an analog output. By using a loopback connection, the program reads the waveform back through an analog input and filters out the noise. The FPGA sends waveform data at various stages of the process to the Real-Time target where it is formatted to display on a chart.

Download: 

10 - Butterworth Filter.zip

Instructions:

1. From the download directory, open Butterworth Filter - sbRIO.lvproj.
2. Expand the directory for the Real-Time target, then the FPGA target.
3. Open and examine the FPGA personality defined by Generation and Filter (FPGA).vi.
4. Open and run Host.vi on the Real-Time target.

For additional help with this example, see the documentation included in the application.

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11. Watchdog Personality 

This VI creates an FPGA personality to emulate a hardware watchdog. If the watchdog timer is not reset prior to a software-defined expiration time (in milliseconds), an indicator will show that the watchdog has timed out.

Download: 

11 - Watchdog Personality.zip

Instructions:

1. From the download directory, open WD Polling – sbRIO.lvproj.
2. Expand the directory for the Real-Time target, then the FPGA target.
3. Open and run WD Polling.vi.

For additional help with this example, see the documentation included in the application.

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12. Watchdog Interrupt 

This application builds off of the FPGA personality created in the previous example. If the watchdog timer is not reset prior to a software-defined expiration time (in milliseconds), an indicator will show that a timeout has occurred. This will trigger an event to execute on a monitoring Real-Time target. This shows how the watchdog can be used to trigger interrupt code. In this example, the Real-Time target simply opens a dialog to indicate a timeout has occurred.

Download: 

12 - Watchdog Interrupt.zip

Instructions:

1. From the download directory, open WD Occurrence – sbRIO.lvproj.
2. Expand the directory for the Real-Time target, then the FPGA target.
3. Open and examine WD Polling.vi on the FPGA target.
4. Open and run the Watchdog Occurence.vi.

For additional help with this example, see the documentation included in the application.

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13. Real-Time FIFO  

This application demonstrates the use of a Real-Time FIFO to communicate data between two loops. The first FIFO in this example contains control information while the second contains waveform data for display. A low priority loop reads waveform data and displays it on a graph while writing data to the control FIFO. A high priority loop writes waveform data to the data FIFO and regulates the waveform according to data on the control FIFO.

Download: 

13 - RT FIFO.zip

Instructions:

1. From the download directory, open RT FIFO Communication – sbRIO.lvproj.
2. Expand the directory for the Real-Time target.
3. Open and run RT FIFO.vi.

For additional help with this example, see the documentation included in the application.

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14. TCP Client and Server 

This application shows how to use TCP communication to transfer streaming data from a Real-Time target to a computer target. A TCP connection is opened between the targets. The data server on the Real-Time target generates waveform data and transfers it to the data client on the computer target.

Download: 

14 - TCP Client and Server.zip

Instructions:

1. From the download directory, open TCP Comm – sbRIO.lvproj.
2. Expand the directory for the Real-Time target.
3. Open and run the Simple Data Server.vi from the Real-Time target. It will wait up to 60 seconds for a connection from the computer target on the specified port.
4. Open and run the Simple Data Client.vi from the My Computer target.
5. Make changes on Simple Data Server.vi to be reflected on the Simple Data Client.vi data plot.

For additional help with this example, see the documentation included in the application.

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15. TCP File Transfer 

This application illustrates a TCP file transfer. A Single-Board RIO FPGA personality is used to generate waveform data. The Single-Board RIO Real-Time target reads a finite number of points from this FPGA generated waveform and writes the data to a spreadsheet file. The file is transmitted via TCP from the Real-Time target to a computer target, which then reads the spreadsheet file and outputs the waveform to a graph.

Download: 

15 - TCP File Transfer.zip

Instructions:

1. From the download directory, open TCP File Transfer - sbRIO.lvproj.
2. Expand the directory for the Real-Time target, then the FPGA target.
3. Open and examine FPGA Personality.vi on the FPGA target.
4. Open and run TCP File Receiver.vi on the computer target. It will wait up to 60 seconds for a connection from the Real-Time target on the specified port.
5. Open and run TCP File Sender.vi on the Real-Time target.
6. View the waveform results on the graph contained in TCP File Receiver.vi.

For additional help with this example, see the documentation included in the application.

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16. Comprehensive Download

Use the following link to download all of the examples found on this page:

Download: 

Additional Examples.zip