The RIO Scan Interface Under the Hood

Publish Date: Jan 09, 2009 | 4 Ratings | 4.00 out of 5 |  PDF

Overview

LabVIEW Real-Time 8.6 introduced a new programming model for CompactRIO that reduces development time and complexity. This functionality is powered by two technologies in LabVIEW, the NI Scan Engine and the RIO Scan Interface. The NI Scan Engine is a new component of LabVIEW Real-Time that scans I/O values into memory at a rate you specify. The RIO Scan Interface is a set of FPGA intellectual property (IP) developed by National Instruments that is downloaded to the CompactRIO FPGA and is responsible for I/O module detection, timing, synchronization, and communication. This paper discusses the architecture and operation of the RIO Scan Interface.

Table of Contents

  1. The NI Scan Engine and RIO Scan Interface
  2. Inside the RIO Scan Interface
  3. I/O Module Timing
  4. Using LabVIEW FPGA with CompactRIO Scan Mode
  5. Conclusion

1. The NI Scan Engine and RIO Scan Interface

The NI Scan Engine and RIO Scan Interface work together to provide access to physical I/O on CompactRIO, directly in LabVIEW Real-Time. This new programming model, known as CompactRIO Scan Mode, allows you to place any supported C Series Module in any slot in your CompactRIO chassis and instantly access I/O directly in LabVIEW Real-Time without FPGA programming or compiling. The RIO Scan Interface, built by National Instruments, exists entirely on the FPGA so you do not need new hardware to support it. The RIO Scan Interface manages the timing, synchronizing, and communication to and from the I/O modules. On the FPGA, a hardware-timed scan is continually updating new I/O values and passing the data to the NI Scan Engine using DMA. The NI Scan Engine reads the I/O values and updates a global memory map, which is accessed in LabVIEW Real-Time via I/O variables. The NI Scan Engine and RIO Scan Interface are tightly synchronized, with the ability to correct phase offsets over time. This implementation provides hardware-timed I/O updates at the pin with less that 500ns of jitter.  

 

Figure 1. The synchronization of the NI Scan Engine and RIO Scan Interface maintain less than 500ns of jitter at the pin

 

A timing signal within the FPGA is asserted when the hardware is busy acquiring data from the I/O modules. The period of this hardware scan is determined by the scan rate you specify in the scan engine properties. At the end of each hardware scan the scan engine transfers I/O data between the controller and the FPGA.

Figure 2. A timing signal within the FPGA determines when I/O data is transferred from the FPGA to the real-time controller

 

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2. Inside the RIO Scan Interface

The RIO Scan Interface contains several components that enable the flexibility and performance it provides. Each I/O module communicates directly with a cartridge controller responsible for detecting the module type and communicating I/O data to and from the module. The cartridge controller is a “soft-core” eight-bit microcontroller, which is instantiated in the FPGA, allowing you to use any supported I/O module without compiling. There are also two prebuilt specialty digital blocks in the RIO Scan Interface, which provide high-speed counter, pulse width modulation (PWM), and quadrature encoder input functionality to any eight channel (or less) digital C Series Module. The specialty digital blocks can be routed to any two slots in the CompactRIO chassis. Additional specialty digital blocks can be added using the LabVIEW FPGA Module. Each cartridge controller communicates with a single cartridge manager, which controls the hardware scan timing, synchronization of I/O modules, and synchronization with the NI Scan Engine. A DMA engine also communicates with the cartridge controllers and cartridge manager to transfer data to and from the real-time controller.

 

Figure 3. The RIO Scan Interface contains several components, all of which are instantiated in the FPGA

 

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3. I/O Module Timing

The convert clocks on all I/O modules are free running when the hardware scan signal is asserted. Each I/O module type has individual conversion timing, and modules of the same type have synchronized conversions. When the hardware timing signal on the FPGA is unasserted the latest I/O conversion value is transferred to the NI Scan Engine. Each module performs as many conversions as possible to provide the most recent I/O values to I/O variables configured for direct I/O access, which bypasses the scan and reads directly from hardware.

 

Figure 4. Input module timing

 

A slow input module may take several hardware scan periods to convert a single channel. In this case the hardware scan triggers a sequence of converts on all channels. No channel values are copied to the scan engine until all channels have finished being converted, then all channel values are transferred together.

 

Figure 5. Input timing for a slow module

 

Output module timing is similar to input module timing, but the conversions are left justified so that output values are written immediately at the beginning of a scan. Each module performs as many updates as possible during the hardware scan, so that values written to I/O variables configured for direct I/O access will update as quickly as possible.

 

Figure 6. Output module timing

 

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4. Using LabVIEW FPGA with CompactRIO Scan Mode

One of the most powerful features of CompactRIO Scan Mode is the ability to choose individual modules to program directly with the LabVIEW FPGA Module. Using this approach the modules you select to program directly with LabVIEW FPGA are removed from the I/O scan and the remaining modules communicate with the RIO Scan Interface. When you compile your LabVIEW FPGA VI, if any I/O modules are configured to use scan mode, then the necessary components of the RIO Scan Interface will be included in the compile. The result is a single bit file that supports the scan mode features for modules configured to use scan mode, as well as your custom FPGA logic that communicates directly with the remaining I/O modules. LabVIEW is intelligent about the compile and only includes the required components of the RIO Scan Interface for a given configuration. For example, if you compile an FPGA VI that only uses one module in scan mode, then only one cartridge controller will be included in the RIO Scan Interface. Specialty digital blocks are also removed if not configured. Therefore, the amount of FPGA space consumed by the RIO Scan Interface, when compiling an FPGA VI, scales with number of modules using scan mode. See the example below in Figure 7.

 

Figure 7. When you access I/O modules in scan mode and directly with LabVIEW FPGA, only the required RIO Scan Interface components are included in the compile

 

In the example depicted in Figure 7, notice that fully functional cartridge controllers are built for slots one and two. As a result, any C Series Module supported in scan mode can be placed in slots one and two without recompiling.

Due to the additional RIO Scan Interface logic that must be compiled when using scan mode and LabVIEW FPGA together, compile times are higher when compared to compiling a VI standalone. Also, the RIO Scan Interface uses two of the three DMA channels that are normally available for use in LabVIEW FPGA.

 

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5. Conclusion

LabVIEW Real-Time 8.6 introduces innovative technologies that reduce development time and complexity. The RIO Scan Interface provide fast access to I/O data direct in LabVIEW Real-Time without FPGA programming, while also allowing you to program selected I/O modules with LabVIEW FPGA for advanced requirements.

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