LabVIEW FPGA Benchmarks for Virtex-5 R Series Targets

1. Introduction

The newest generation of R Series multifunction RIO boards feature Virtex-5 FPGA chips for enhanced custom triggering and onboard processing capabilities. The number of “system gates” has traditionally been a way to compare FPGA chips to ASIC technology, but does not truly describe the number of individual components inside an FPGA. This is one of the reasons why Xilinx does not specify a number of gates for the new Virtex-5 family. How then, do the new Virtex-5 R Series targets compare to previous Virtex-II based devices? In reality, there is no single specification that tells the whole story. The new Virtex-5 FPGA architecture itself is quite different, and trying to look at individual specs is like a comparison of apples and oranges.

Virtex-5 FPGAs are optimized to execute faster and more efficiently using the single-cycle timed loop structure in LabVIEW FPGA. The fundamental building blocks for implementing digital logic inside FPGA chips are called slices, and each slice is composed of flip-flops and look-up tables (LUTs). Previous-generation Virtex-II FPGAs use 4-input LUTs for up to 16 combinations of digital logic values. The new Virtex-5 FPGAs use 6-input LUTs for up to 64 combinations, increasing the amount of logic that you can implement per slice.  The single-cycle timed loop structure in LabVIEW FPGA takes advantage of six-input LUTs for substantially improved resource utilization. This means you can optimize more LabVIEW FPGA code to fit within Virtex-5 FPGAs and perform more operations per clock cycle. In addition, the slices themselves are placed in closer proximity to each other to reduce the propagation delay of electrons and increase overall execution rates.

For more information on understanding specifications and how FPGAs work, read the “FPGAs - Under the Hood” white paper.

Without having to understand the low-level details of FPGA architectures, we can examine LabVIEW FPGA benchmarks to see examples of how Virtex-5 R Series targets provide bigger and faster FPGAs. 

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2. Virtex-5 Benchmarks for Size

In order to compare size differences between Virtex-II and Virtex-5 FPGAs, it is important to get a feel for how much LabVIEW code can fit on each target.  Figure 1 shows the piece of graphical code used to benchmark the amount of general logic resources.

Figure 1. Section of code used for General Logic Benchmarking

We took this code, which primarily uses the logic resources (Flip-Flops and LUTs), and tested to see how many times it would fit on each target.  We used a single-cycle timed loop to make the most of the new 6-input LUTs on Virtex-5 FPGAs.  This piece of code includes IP cores, (or function blocks) for simple event counting, pulse-width modulation and quadrature encoder reading.  None of these functions require any specialty resources like multipliers or embedded block RAM.  This piece of code fit 22 times on a PXI-7831R, which has a Virtex-II 1M gate FPGA.  Figure 2 shows the resulting block diagram, with all code within a single single-cycle timed loop structure.

Figure 2. LabVIEW FPGA block diagram for a PXI-7831R, with 22 instances of general logic code.

Table 1 shows the maximum number of time the benchmarking code fits into four different LabVIEW FPGA targets.

Table 1:  Maximum number of benchmark code instances for each FPGA target.

Figure 3 shows a chart that takes the same data in Table 1, and directly compares the Virtex-5 LX30 with a 1M Gate Virtex-II FPGA, and the Virtex-5 LX50 with a 3M gate Virtex-II FPGA.

Figure 3.  Direct size comparison of new Virtex-5 FPGAs with legacy Virtex-II FPGAs.

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3. Virtex-5 Benchmarks for Speed

Another important benefit that the new Virtex-5 architecture provides is the ability to compile code at faster rates, increasing the processing capabilities of LabVIEW FPGA hardware. One way to quantify this improvement in execution speed is to take a specific piece of code within a single-cycle timed loop and ramp up the clock rate until the compilation process can no longer meet timing requirements.  Figure 4 shows the single-cycle timed loop that was used to compare Virtex-II targets to Virtex-5 targets. 

Figure 4: LabVIEW FPGA block diagram of ten adders, serially configured within a single-cycle timed loop structure.

The graphical code within this loop serially adds eleven 8-bit numbers together, using ten addition functions in LabVIEW.  While this is not the most efficient way to add eleven numbers together, we can use this code to assess the relative speed differences between each target and benchmark the maximum clock rates.  Table 2 shows the results of these speed benchmarks.

Table 2:  Maximum clock rate of ten serial adders for each FPGA target.

As shown in Table 2, these speed benchmarks demonstrate that the new Virtex-5 FPGA architecture is approximately twice as fast as legacy Virtex-II FPGAs.  The chart shown in Figure 5 compares the Virtex-II 1M gate FPGA to the Virtex-5 LX30 FPGA.

Figure 5.  Direct speed comparison of new Virtex-5 LX30 FPGAs with legacy Virtex-II 1M Gate FPGA.

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4. Virtex-5 Benchmarks for Processing

Virtex-5 FPGA chips provide significant processing performance improvements compared to Virtex-II chips. Several factors can play into the processing power of an FPGA chip such as multipliers, logic resources, and execution speed. This makes it difficult to compare by only looking at the specs and one approach is to benchmark with common processing algorithms. Fast fourier transforms (FFTs) are a way to get frequency information from digitized signals. Our benchmark focuses on FFT throughput, or the maximum number of FFTs calculated per second, on each FPGA target.

Figure 6.  LabVIEW FPGA code for benchmarking FFT throughput.

The code shown in Figure 6 uses the new FFT function released in LabVIEW 8.6. Since R Series devices sample at 16-bit resolution, we chose 16-bit data types and 1024-point FFTs to emulate real-world use cases. We use parallel FIFO loops to feed and retrieve data from the FFT processing loop in order to emulate data being acquired or transferred to the device through DMA. The FFT Express VI includes a configuration option to choose between optimizing for size, which uses less logic and multiplier resources, or optimizing for speed, which uses more resources. The methodology used to maximize throughput for each target is as follows:

1. Add parallel high-speed FFT loops until resources overmap.
2. Add size-optimized FFT loops in parallel with the streaming FFT loop(s) until resources overmap.
3. Increase the execution rate of the VI until timing fails.

Table 3 shows the results of the benchmarks.

Table 3:  Maximum FFTs per second for each FPGA target.

Looking at Table 3, the results show clear processing performance improvements in Virtex-5 FPGA chips over Virtex-II FPGA chips. Looking specifically at the Virtex-II 3M gate vs. Virtex-5 LX50, while the two appear to have comparable logic resources (as shown in the previous size benchmarks), the LX50 achieves double the processing performance because of faster execution rates provided by the Virtex-5 architecture. The Virtex-5 LX85 and LX110 have even more available multiplier and logic resources and as a result have the best processing performance. 

Figure 6.  16-bit 1024-point FFT throughput benchmarks using LabVIEW FPGA FFT Express VI.

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5. Additional Resources

View pricing and specifications for R Series multifunction RIO

R Series Multifunction RIO Frequently Asked Questions (FAQ)

FPGAs Under the Hood Whitepaper

NI LabVIEW FPGA