Opens and Shorts Testing Reference Design

Publish Date: Sep 08, 2013 | 14 Ratings | 3.71 out of 5 | Print

Overview

This document will discuss the technical details of an opens and shorts test system created in PXI. To learn more about the hardware components, click here. To learn more about the software components, click here.

Table of Contents

  1. Section 1: Hardware Setup
  2. Section 2: Software Setup

Although opens and shorts test can be conducted for a wide range of devices, it is most common in semiconductor validation test. This paper will describe, in detail, the process of testing for opens and shorts on a CMOS chip.

Before delving in to the technical details of opens and shorts test, we must first understand its relevance with regards to semiconductor validation. Semiconductor validation is generally segmented in two parts, structural and functional. Structural tests ensure that the chip has been built correctly. Functional tests determine whether the chip meets design specifications and performs as intended in its final environment. Opens and shorts test checks for faults in the protection diode circuitry of semiconductor chips. It is therefore a structural test.

The figure below represents a typical CMOS chip. As can be seen, each pin has a network of protection diodes and CMOS transistors.

Figure 1: Internal Circuitry of a CMOS Chip

CMOS transistors on each input pin act like switches by allowing current to flow from VDD (supply voltage for the chip) into the DUT circuitry and from the DUT circuitry to VSS (ground). CMOS transistors can be damaged if an overvoltage condition is induced at an input or output pin. To protect these devices, two diodes are placed at each signal pin (refer to Figure 1). The first sits between the signal pin and VDD and the second between the signal pin and VSS. If a positive overvoltage greater than VDD is applied on any pin, the VDD diode becomes forward-biased, allowing current to flow between the signal pin and VDD. Similarly, if a negative overvoltage greater than VSS is applied on any pin, the VSS diode becomes forward-biased, allowing current to flow between the VSS and the signal pin. This way, the protection diodes prevent damage to the CMOS transistors and DUT circuitry in overvoltage conditions. Both the VDD and VSS protection diode must be tested for open and short conditions to ensure their correct operation. An open condition may occur if a protection diode is missing or is functioning incorrectly. A short condition may occur if a direct connection exists:

  • Between the pin and VDD
  • Between the pin and VSS
  • Between the pin and another signal pin

Each of these short-circuit failure modes prevent the correct operation of the device. Opens and shorts test checks for all the aforementioned failure modes.

Note: CMOS integrated circuits are based on FET technology, and so often use the VDD/VSS terminology for positive supply voltage /negative supply voltage (ground). These terminals can also be documented as VCC/Gnd.

1. Section 1: Hardware Setup

Test Setup

The test set up for opens and shorts is separated into two routines: testing the VDD protection diode and testing the VSS protection diode.

Testing the VDD Protection Diode

In order to detect an open or short across the VDD protection diode of a signal pin, connect VSS, VDD, and all other signal pins to SMU ground and force a minimal current (i.e. 100 μA) into the signal pin. If the VDD protection diode operates correctly, then it will become forward-biased and the current will flow between the signal pin and VDD (see Figure 2).

 

Figure 2: Testing the VDD diode (switching not shown)

By measuring the voltage drop across the forward-biased VDD diode, we can determine whether it is functioning correctly. If the voltage measured between the signal pin and ground is close to 0 V (or ground), then there are one or more short-circuits between the signal pin and ground through VSS, VDD, and/or another signal pin. If the voltage measured between the signal pin rails or climbs to a potential that is higher than an acceptable forward-biased voltage drop, then there is an open circuit between the signal pin and ground. If the measured voltage is an acceptable forward-biased voltage drop, then the VDD protection diode is operating correctly. Table 1 shows an example of VDD protection diode test results and the resulting pass/fail specifications.

Voltage Reading at Signal Pin

Test Result

Less than +0.2 V

Fail: Shorted

In between +0.2 V and +1.5 V

Pass

Greater than +1.5 V

Fail: Open

Table 1: VDD Protection Diode Test Specifications

Note: No current (other than a small amount of leakage current) flows through the VSS protection diode because it will be reverse-biased.

Note: The acceptable forward-biased voltage drop is typically dependent upon the material from which the semiconductor diode is made. However, manufacturing techniques may also be used to lower the forward-biased voltage drop. The forward-biased voltage drop of a silicon diode is generally accepted to be 0.65 V. The exact voltage drop is dependent on the current flowing through the diode’s p-n junction, the temperature of the junction, and several physical constants. The relationship between the forward-biased voltage drop, the applied current, and the associated variables is shown below in Figure 3, commonly known as the diode equation:

 

Figure 3: The Diode Equation

The variables in the diode equation are described below. ID = Diode current (A) IS = Saturation current (A) VD = Voltage drop across diode (V) N = Ideality coefficient, between 1 and 2 Vt = Thermal voltage (V), around 25.85 mV at room temperature The voltage between the signal pin and ground would be close to 0 V, and the test result would be Fail: Shorted. If the other signal pins were not all grounded, current would still flow through the forward-biased VDD protection diode (as shown in Figure 2), and the test result would be Pass.

Testing the VSS Protection Diode

The process for testing the VSS diode is the same as that for testing the VDD diode. All pins including VSS and VDD are connected to SMU ground. This time however, a negative current of the same value (i.e. -100 μA) is forced into the signal pin. If the VSS protection diode operates correctly, it will become forward-biased and current will flow between VSS and the signal pin (see Figure 4).

Figure 4: Testing the VSS diode (switching not shown)

Note: No current (other than a small amount of leakage current) flows through the VDD protection diode because it will be reverse-biased.

By measuring the voltage drop across the forward-biased VDD diode, we can determine whether it is functioning correctly. Table 2 shows the test parameters for the VSS protection diode.

Voltage Reading at Signal Pin

Test Result

Greater than -0.2 V

Fail: Shorted

In between -0.2 V and -1.5 V

Pass

Less than -1.5 V

Fail: Open

Table 2: VSS Diode Test Specifications

Automated Test Setup

Two common hardware configurations are available to perform an open/shorts test. First, an external switching system front end and programmable source measure unit can be utilized to automate the VDD and VSS protection diode testing. The switching system can scan through pre-configured states, creating the required current and ground paths to the VDD, VSS, and signal pins of the semiconductor device. The source measure unit can force the required currents and measure the resulting voltages from each signal pin to ground (see Figure 5). Second, the PXIe-6556 can be used in addition to the switching system or by itself on the digital pins using the PPMU capabilities of the card. Option one is discussed in detail below.

Figure 5a: Opens/Shorts automated test set up using SMU and MUX

 


Figure 5b: Opens/Shorts automated test set up using HSDIO

The following steps outline the process for conducting opens and shorts test using the SMU and switch combination above:

Step 1: Ground All Pins

In order to connect the SMU to the DUT through the FET switch, a matrix topology is used with pins from the SMU connected to rows in the matrix and pins from the chip connected to columns.

Grounding all pins on the DUT is accomplished by closing all the connections on the matrix that route the ground of the PXI-4130 SMU to the pins on the DUT. Connections from the PXI-4130 SMU Low pin to VDD and VSS is done directly through a cable instead of through the switch. This is because VDD and VSS pins are always connected to the SMU Low pin. While all signal pins are initially connected to SMU Low, they are sequentially connected to the SMU measurement channel and are therefore connected to the SMU through the matrix switch.

It is important to not only connect VSS and VDD to ground. All other signal pins should be connected to ground before testing the protection diodes. Grounding all the other signal pins ensures that any signal pin-to-signal pin short-circuits is detected. See Figure 6 for further explanation. When a short is detected between two signal pins, the voltage between the pin under test and SMU low should be outside the acceptable range listed in tables 1 and 2 (ideally 0V) and the test should fail. If the other signal pins were not all grounded, current would still flow through the forward-biased VDD protection diode and the test result would be Pass. See Figure 6 below.

Figure 6: Grounding pins is essential for detecting shorts

Step 2: Set a Voltage Clamp on the SMU at 3 V

In order to the limit voltage produced during open circuit conditions, an upper limit voltage clamp is set on the SMU. If no clamp is set and the circuit is open, the SMU will measure a very high voltage value. This can damage the chip circuitry. On the PXI-4130, the voltage clamp level is set in software to a value of 3 V. 3 V is an acceptable value because it is above the test limit for detecting open circuits (1.5V) and is within the specifications of most CMOS chips.

Step 3: Force ±100uA from SMU and Measure the Resulting Voltage

The SMU forces ±100 µA of current into each signal pins’ diodes one at a time and measures the resulting voltage. Each pin is sequentially connected to the SMU via the matrix switch. For this test a voltage of approximately ±0.65 V (the voltage drop across a forward-biased diode) is expected. The voltage resulting from the forced current is measured and compared to the test specification tables in order to determine the final test results.

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2. Section 2: Software Setup

The software for this opens and shorts system is developed using NI LabVIEW and NI Switch Executive. LabVIEW is used as the primary Application Development Environment (ADE) while Switch Executive is used to configure routes on the high-density matrix.

The following software versions were used to implement the Opens and Shorts Semiconductor Test:

LabVIEW 8.5Graphical Programming Environment

Switch Executive 2.1.1Switch Management Software

The LabVIEW code described in this document can be downloaded from the link at the end of this document.

Note: Functional blocks in the LabVIEW graphical programming language are known as ‘Virtual Instruments’ or ‘VIs’. The acronym ‘VI’ will therefore be used when describing procedures in this section.

As stated previously, the Opens and Shorts Test can be separated into two routines, a) testing the VDD protection diode, and b) testing the VSS protection diode. Both routines can be performed using the same hardware connections, and the only difference in programming the routines can be as simple as changing the direction of the SMU’s forced current. Due to these similarities, this document simply outlines an example demonstrating how to test the VSS protection diode. This test routine can be duplicated and slightly altered to test the VDD protection diode. Details on necessary alterations are provided at the end of the document.

The steps to test the VSS protection diode are the following:

  1. INitialize, configure, and enable SMU output
  2. Initialize the switching hardware and connect all DUT pins to ground
  3. Iterate through the signal pins using the 5544 crosspoint FET matrix
    1. Disconnect the signal pin under test from ground
    2. Connect the SMU to the signal pin under test
    3. Measure the voltage between the signal pin under test and ground
    4. Conduct analysis on voltage measured to determine test result
    5. Disconnect the SMU from the signal pin under test
    6. Reconnect the signal pin under test to ground
  4. Disable the output of the SMU and close the SMU session handle
  5. Disconnect all signal pins from the switching hardware and close the NISE session handle

Initialize the SMU, configure, and enable the output of the SMU

Initialize, configure, and enable the output of the PXIe-4141 SMU using the NI-DCPower API in LabVIEW. Refer to Figure 7 for a picture of the block diagram code.

Figure 7: Initializing, Configuring, and Enabling the SMU Output in LabVIEW

The SMU’s resource name is fed to the Initialize VI to initialize the SMU and to provide a SMU session handle. The SMU session handle is then passed to all subsequent NI-DCPower VIs. Next, channel 1 of the SMU is configured for DC Current, which is what it will be sourcing to conduct the test. The NI-DCPower configuration VIs can be wired in any order, as long as all the parameters are set before enabling the SMU output. The parameters that are required to be fed include the current level, the current level range, the voltage limit, and the voltage limit range.

The step following the Initialize VI is the niDCPower property node. This step instructs the SMU to automatically determine and set current level and voltage limit ranges based on the current level and voltage limit inputs. The VI following the property node confirms that the SMU is to be used in DC Current mode. Next, the current level is set to -100 μA (to test the VSS protection diode, channel 1 is configured such that the current flows into the SMU and the VSS protection diode is forward-biased), and the voltage limit, or voltage clamp, is set to 3 V (equivalent to ±3 V).

Lastly, a Boolean true inputted to the Configure Output Enabled VI enables the output of the SMU, committing the configuration parameters to the device and commencing the -100 μA flow of current through channel 1 of the SMU.

Initialize the switching hardware and connect all DUT pins to ground

Initialize the switching hardware and set it to a state where VDD, VSS, and all the DUT’s signal pins are connected to ground. There are multiple ways to control switches using LabVIEW, but the best way to program switching hardware as a system is with the NI Switch Executive API. Refer to Figure 8 for a picture of the block diagram code.

Figure 8: Initialize the Switching Hardware and Connect all the DUT Pins to Ground

The NI Switch Executive (NISE) Virtual Device Name is inputted to the Open Session VI to open session handles to all the switches in the system. NI Switch Executive stores these session handles in one NISE session handle that is passed to all subsequent NISE VIs. The ‘Disconnect All’ VI disconnects all connections on every switch device managed by the NI Switch Executive session, thereby setting the switch system configuration in a known state where no switch routes are connected. Lastly, all routes in the GND to DUT route group are connected, which results in the switching hardware being set to a state where VDD, VSS, and all the DUT’s signal pins are connected to ground.

To learn more about what an NI Switch Executive Virtual Device is and how to create one, view the 7-minute NI Switch Executive demo which is linked at the end of this document.

Iterate through the signal pins, testing one at a time

Iterate through the DUT signal pins using a LabVIEW ‘For Loop’. Within the ‘For Loop’, use NI Switch Executive VIs to disconnect the DUT signal pin under test from ground and to connect the DUT signal pin under test to channel 1 of the SMU. Use NI-DCPower VIs to measure the voltage from each DUT signal pin to ground. Before moving on to the next iteration of the For Loop, disconnect the DUT signal pin under test from channel 1 of the SMU and reconnect it to ground (see Figure 9).

Figure 9: Disconnect GND, Connect SMU, Measure, Disconnect SMU, and Reconnect GND

In the above figure, we:

  1. Disconnect the signal pin under test from ground
  2. Connect the SMU to the signal pin under test
  3. Measure the voltage between the signal pin under test and ground
  4. Determine the test result based on the voltage measurement
  5. Disconnect the SMU from the DUT signal pin under test
  6. Reconnect the DUT signal pin under test to ground

The process of disconnecting and reconnecting of DUT signal pins is done using route groups which are created in NI Switch Executive. Route Groups are used to put the switch matrix in to a desired state. To learn more about what a route group is and how to create one view the 7-minute NI Switch Executive demo linked at the end of this document. The first route group contains routes connecting the DUT signal pins to ground, and the second route group contains routes connecting the DUT signal pins to channel 1 of the SMU (see Figure 10).

Figure 10: Set up Route Groups to Simplify Indexing the Correct DUT Signal Pin

Next, the NI Switch Executive configuration API in LabVIEW, which provides full programmatic access to all NI Switch Executive features, is used to extract individual route names from all route groups. The result will be two string arrays comprised of the routes from Route Group 1 and Route Group 2 (see Figure 11).

Figure 11: Array Output Using NI Switch Executive Configuration API

Passing these arrays into a For Loop will automatically index the arrays. For example, on the first iteration of the loop, the indexed routes to be connected and disconnected inside the loop are DUT_Signal_Pin0_to_GND and DUT_Signal_Pin0_to_SMU_Channel1. On the second iteration of the loop, the indexed routes are DUT_Signal_Pin1_to_GND and DUT_Signal_Pin1_to_SMU_Channel1. This will continue until the arrays have indexed each element. You are not restricted to this naming scheme. You can enter your specific array names in to the ‘Route Group 1’ and ‘Route Group 2’ control fields of the ‘Switch Exec for OS’ VI.

Based on the pass/fail specifications of the DUT, determine if the voltage measurement indicates the VSS protection diode on the DUT signal pin under test has passed, failed open, or failed because of a short-circuit (see Figure 12).

Figure 12: Determine Test Result Based on the Voltage Measurement

After making the voltage measurement and determining the test result, disconnect channel 1 of the SMU from the DUT signal pin under test and reconnect the pin under test to ground.

Disable the output of the SMU and close the SMU session handle

Use NI-DCPower VIs to disable the output of the SMU and close the SMU session handle. Refer to Figure 13 for a picture of the block diagram code.

Figure 13: Disable the SMU Output and Close the SMU Session Handle

A Boolean false inputted to the Configure Output Enabled VI disables the output of the SMU, ceasing the -100 μA flow of current through channel 1. The Close VI closes the SMU session handle and reallocates the SMU resources that were previously reserved.

Note: If power output is still enabled when you call the Close VI, channel 1 will remain in its current state and continue sinking current.

Disconnect all signal pins from the switching hardware and close the NISE session handle

Use NI Switch Executive VIs to disconnect VDD, VSS, and the remainder of the signal pins from the switching hardware and close the NISE session handle. Refer to Figure 14 for a picture of the block diagram code.

Figure 14: Disconnect All Signal Pins and Close the NISE Session Handle

The Disconnect All VI once again disconnects all connections on every switch device managed by the NI Switch Executive session, thereby setting the switch system configuration in a known state where no switch routes are connected. The Close Session VI closes session handles to all the switches in the system. Although not required, it is often helpful to include an error handler. If an error occurs, the VI returns a description of the error and optionally displays a dialog box with the error information.

Modifying the Code to Test the VDD protection diode

To modify the VSS protection diode test, the SMU must first be disabled, and then the configuration should be changed to force 100 μA instead of -100 μA on channel 1 before re-enabling the SMU. The For Loop can perform the exact same connections and disconnections, taking measurements and determining the test results.

Combining the VSS and VDD protection diode tests

Determining the final result for each DUT signal pin can be done by combining the results of the VSS and VDD protection diode tests. A final result of pass can only be determined if both protection diodes pass their respective tests. There are multiple methods to display test results, including but not limited to a) passing Booleans into an LED array, and b) formatting and displaying string clusters in an array.

Links:

  1. DC Parametric Semiconductor Validation Test Reference Architecture
  2. DC Parametric Semiconductor Validation: Hardware Components
  3. DC Parametric Semiconductor Validation: Software Components
  4. Open and Short Circuit Test
  5. Power Consumption Tests (IDD, IDDQ)
  6. Input Voltage Threshold Test (VIL, VIH)
  7. Input Leakage Test (IIL, IIH)
  8. Output Voltage Level Test (VOL, VOH)
  9. Output Short Circuit Test (IOS)
  10. NI PXIe-4141 4-Channel Precision SMU With NI SourceAdapt Technology
  11. NI PXIe-6556 200 MHz HSDIO with PPMU
  12. NI PXI-2535 544-Crosspoint FET Matrix Switch

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