Timing and triggering flexibility is a fundamental part of selecting DAQ hardware. Instead of a fixed ASIC for controlling device functionality, R Series devices use an FPGA-based system timing controller to make all analog and digital I/O configurable for application-specific operation. By creating custom personalities, a single piece of hardware can meet the most demanding requirements and be easily reconfigured for future applications.
Figure 1. R Series multifunction RIO devices come in multiple PC form factors.
Using R Series devices, you can create a custom hardware personality without any prior background or expertise in low-level hardware design. A personality is essentially a LabVIEW FPGA application that has been compiled into a bitfile containing FPGA configuration information. Once the bitfile has been generated, a personality no longer requires the LabVIEW FPGA Module and can be accessed in LabVIEW for Windows or LabVIEW Real-Time using the NI-RIO driver. The personality can also be downloaded to nonvolatile flash memory on the R Series device itself and configured to load on power up.
2. Use a Custom Personality
The LabVIEW FPGA Module takes LabVIEW block diagrams and implements them to execute in silicon on an FPGA chip. R Series hardware is specified in the LabVIEW Project Explorer and when the run arrow is selected a LabVIEW FPGA VI begins to compile into a personality bitfile. Once the bitfile has been generated, all front panel objects (controls and indicators) of the LabVIEW FPGA VI are represented as registers on the FPGA chip and can be accessed from a host application using the NI-RIO driver.
Figure 2 shows the block diagram for a LabVIEW FPGA application that has been compiled into a bitfile. This is used as the example custom personality in this tutorial.
Figure 2. This example custom personality includes multirate sampling and four 64-bit simple event counters.
This example personality samples two analog input channels independently and also includes four 64-bit simple event counters. Each analog input loop references a separate digital I/O line for triggering and acquires a finite number of samples on every rising edge. On R Series multifunction RIO devices, the analog value is digitized when the analog FPGA I/O Node executes. The resulting sample is then immediately transferred across the bus to host memory using a DMA FIFO Node. Sampling different analog channels at independent rates is not possible on typical DAQ hardware.
Figure 3 shows the front panel of the same LabVIEW FPGA VI.
Figure 3. Front Panel for Example Custom Personality
The front panel controls and indicators are important because they become the only access you have to a compiled LabVIEW FPGA block diagram. As mentioned earlier, all front panel objects are converted to hardware registers on the FPGA. This example uses controls to configure the number of samples and sample period (in microseconds) for the two analog input channels. The 64-bit value of counter registers is also shown on the front panel and can therefore be read from the host application. The following sections focus on host application development for this example DAQ personality.
For more information on LabVIEW FPGA programming for DAQ applications, see Advanced Data Acquisition Techniques With NI R Series Multifunction RIO.
3. Build a Host VI for a Compiled LabVIEW FPGA Personality
After the custom personality has been created, you can interact with hardware registers by developing a host application using the NI-RIO driver. NI-RIO driver software is included with all R Series multifunction RIO hardware and automatically installs the FPGA host interface palette shown in Figure 4.
Figure 4. Open FPGA VI Reference.vi on FPGA Host Interface Palette
The Open FPGA VI Reference.vi function on the FPGA interface palette opens a reference to the R Series device, as well as the LabVIEW FPGA VI or bitfile.
Figure 5. Selecting a Compiled LabVIEW FPGA Bitfile
To select your LabVIEW FPGA VI or bitfile, right-click on the Open FPGA VI Reference.vi and select Configure Open FPGA VI Reference… Select your bitfile or LabVIEW FPGA VI that you want to run and click OK.
Next, the Read/Write Control.vi function is used to read or write to any LabVIEW FPGA front panel control or indicator.
Figure 6. Read/Write Control.vi on FPGA Host Interface Palette
Once the LabVIEW FPGA VI reference is wired to the input of this function, a list of all front panel controls and indicators is populated, similar to LabVIEW property nodes. Reading this function in a loop polls registers on the FPGA at the loop rate. The Read/Write Control.vi function is efficient at passing single data values to and from the compiled LabVIEW FPGA VI.
Figure 7. Writing to FPGA VI Front Panel Objects From the Host Interface Application
A major difference between traditional multifunction DAQ with the NI-DAQmx driver and R Series devices is the way that DMA data transfer is implemented. The NI-DAQmx driver abstracts out all transfers from the device to the host computer. This must be completely programmed in LabVIEW for all R Series devices. Reading or writing to DMA channels on R Series hardware is accomplished using the Invoke Method.vi function. Once the input of this function is wired with a LabVIEW FPGA VI reference, all DMA channels are populated in the menu list and can be selected as shown in Figure 8.
Figure 8. Invoke Method.vi on FPGA Host Interface Palette
The amount of RAM allocated for the host-side buffer is configured by selecting Configure in the submenu. By default, the buffer size is 10,000 elements or twice the size of the FPGA FIFO buffer, whichever is greater.
Reading a DMA FIFO produces an array values of the configured data type. In this example, we used unsigned 32-bit integers. In addition, the Method Node provides the number of elements remaining in the PC buffer. Data must be converted back to signed integer 16 (I16) data type and scaled accordingly, as shown in Figure 9.
Figure 9. Scaling Data Values From DMA FIFOs
For more information on creating DMA FIFOs in LabVIEW FPGA, see Using DMA FIFO to Develop High-Speed Data Acquisition Applications for Reconfigurable I/O Devices.
Finally, the reference must be closed using the Close FPGA VI Reference.vi function in the FPGA interface palette.
Figure 10. Close FPGA VI Reference.vi on FPGA Host Interface Palette
The figure below is the final block diagram for a host application that streams data from an analog input channel and monitors the value of four 64-bit simple event counters.
Figure 11. Block Diagram of Final Host Application VI
Figure 12. Front Panel of Final Host Application VI
You might remember that this example personality is actually reading two different analog input channels at two different rates. The following figure is the block diagram of a different host application that reads both analog input loops at different rates.
Figure 13. Block Diagram of Second Host Application VI
Figure 14. Front Panel of Second Host Application VI
This shows how many different host applications can be created for the same personality, depending on what functionality is required.
4. Download Custom DAQ Example Personalities and Documentation
8 analog input channels, 8 analog output channels, 4 counters, and 16 digital I/O lines
This custom personality is a balanced analog I/O board that has eight simultaneously sampled analog input channels and eight simultaneous analog output channels. In addition, this personality also includes four simple event counters with debounce filtering and 16 static DIO lines.
Multirate Analog Output
8 analog output channels with multiple update rates
This personality uses all eight analog outputs of an R Series device. Each analog output channel can be used in either streaming mode or regeneration mode. In streaming mode, new samples are continuously sent from the host VI to the FPGA and are output as they are received. In regeneration mode, samples are loaded into a block of onboard memory and the FPGA application continuously indexes through these samples without any further host interaction. This example personality can update groups of analog output channels at different rates, which is not possible with other DAQ devices.
PWM Input and Output
16 PWM channels configurable for input or output
The PWM personality was designed to target high-channel-count needs for both PWM output and input. Currently, there is not a DAQ device capable of more than four PWM outputs. The current solution is to use multiple DAQ boards capable of PWM and synchronize their outputs. This personality alleviates that need by creating a custom R Series personality to have 16 PWM channels configurable for input or output. The attached host example code uses 12 PWM outputs and four PWM inputs.
64-bit Counter Board
Sixteen 64-bit simple event counters (40 MHz)
This example personality features 16 simple-event counters, each with 64-bit resolution. With the ability to count up to 264–1, these counters can essentially count forever. In addition to being the highest in resolution and channel count, this personality gives you the ability to specify the terminal count, generates output pulses when the terminal count is reached, and provides filtering capability to remove noise and glitches from the source signal.
8 quadrature encoders configured for input and output
This example personality uses 18 digital lines for six quadrature encoder inputs and six digital lines for two quadrature encoder outputs. The personality was designed to target high-channel-count needs for both quadrature encoder output and input.
While fixed ASIC chips such as the NI-STC3 can meet the majority of data acquisition requirements, complete flexibility and customization can be achieved only with the reconfigurable, FPGA-based I/O timing and control of R Series multifunction RIO devices. By creating custom personalities, a single piece of hardware can meet the most demanding requirements and be easily reconfigured for future applications. The LabVIEW FPGA Module makes triggering and synchronization tasks as simple as graphically drawing the block diagram to do exactly what you need. Once the personality has been compiled, it can be accessed from a host application with the NI-RIO driver. Whether it is multirate sampling, custom counter operation, or onboard decision making at 40 MHz, custom R Series personalities deliver board-level customization to commercial off-the-shelf hardware.